IGBT Accumulation Areas Reduce Electromagnetic Noise
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Solution Overview
Problem
Conventional insulated gate bipolar transistors (IGBTs) experience high electromagnetic noise due to large voltage reduction rates during turn-on, which is attributed to significant displacement currents flowing through the gate electrode, leading to shorter turn-on times and increased noise.
Innovation Solution
The semiconductor device incorporates a semiconductor substrate with a drift region, emitter, base, and trench sections, including multiple accumulation areas with specific doping concentrations and arrangements to reduce displacement currents and electromagnetic noise, achieved through the strategic placement and doping of gate and dummy trench sections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the turn-on time of the IGBT is shortened to improve switching speed, then the voltage reduction rate (dV/dt) increases, but electromagnetic noise becomes larger
Solution Approach 1:
The drift region is segmented into multiple accumulation areas with different doping concentrations (first, second, and third accumulation areas at different depths), which divides the displacement current path into multiple zones. This segmentation allows controlled reduction of displacement current while maintaining fast turn-on performance, thereby reducing electromagnetic noise without sacrificing switching speed.
Solution Approach 2:
Different regions of the drift region are assigned different doping concentrations to achieve local optimization. The first accumulation area (closest to gate) has higher doping concentration to reduce displacement current, while deeper areas have progressively lower concentrations to maintain voltage blocking capability. This local quality variation reduces electromagnetic noise while preserving fast switching characteristics.
2Use of energy by moving object
If the doping concentration of the drift region is increased to reduce on-voltage, then the breakdown voltage capability decreases
Solution Approach 1:
The invention changes the doping concentration parameter across different depths of the drift region, creating a gradient structure with three distinct accumulation areas. This parameter variation allows the device to achieve low on-voltage (through higher doping near the gate) while maintaining high breakdown voltage capability (through lower doping in deeper regions), thus resolving the trade-off between conduction and blocking performance.
Solution Approach 2:
The solution transitions from a uniform doping structure to a multi-layered vertical structure with doping concentrations varying in the depth dimension. By introducing this vertical dimensionality with graded doping (first, second, and third accumulation areas at different depths), the patent simultaneously achieves low on-voltage and high breakdown voltage, overcoming the traditional single-parameter limitation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses displacement currents and electromagnetic noise during low-current turn-on, reducing the voltage reduction rate and improving the trade-off between on-voltage and turn-off loss in IGBTs.
Implementation Method 1
the larger a displacement current that flows in a gate electrode of the IGBT during a low-current turn-on
Implementation Method 2
The multiple accumulation areas each may include a region having a doping concentration of the first conductivity type higher than the doping concentration of the first conductivity type of the drift region
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, an emitter region, a base region and multiple accumulation areas, and an upper accumulation area in the multiple accumulation areas is in direct contact with a gate trench section and a dummy trench section, in an arrangement direction that is orthogonal to a depth direction and an extending direction, a lower accumulation area furthest from the upper surface of the semiconductor substrate in the multiple accumulation areas has: a gate vicinity area closer to the gate trench section than the dummy trench section in the arrangement direction; and a dummy vicinity area closer to the dummy trench section than the gate trench section in the arrangement direction, and having a doping concentration of the first conductivity type lower than that of the gate vicinity area.