IGBT Master-Slave Power Factor Correction Circuit
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Solution Overview
Problem
Existing power factor correction circuits, particularly those using MOS field-effect transistors, are not suitable for large-current applications due to increased conduction losses and reverse recovery currents in diodes, which can lead to reverse voltage application to switching elements.
Innovation Solution
A switching power supply circuit employing insulated gate bipolar transistors (IGBTs) with a master and slave configuration, where the slave IGBT is brought into conduction after a predetermined period, and a second diode is used in parallel to the slave IGBT to mitigate reverse voltage application, along with a capacitor to reduce parasitic capacitance charging currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a MOS field-effect transistor is used as a switching element in non-patent literature 1, then the power factor correction circuit can operate, but it is not suitable for large-current purposes due to increased conduction losses
Solution Approach 1:
The patent changes the switching element from MOS field-effect transistor to insulated gate bipolar transistor (IGBT), which has different electrical parameters including lower on-state voltage drop and higher current handling capability, thereby reducing conduction losses in large-current applications
2Loss of energy
If a diode having a low forward drop voltage is used to reduce conduction loss, then conduction efficiency improves, but reverse recovery characteristics worsen causing reverse recovery current flow
Solution Approach 1:
The patent connects a capacitor in parallel with the diode to utilize the reverse recovery current phenomenon. The capacitor absorbs the reverse recovery current, preventing it from flowing through the switching element, thereby converting the harmful reverse recovery effect into a manageable condition that protects the circuit
3Productivity
If reverse recovery current flows in the diode, then conduction efficiency is maintained, but reverse voltage is applied to the switching element causing potential damage
Solution Approach 1:
The patent places a capacitor in parallel with the diode to provide a cushioning effect before reverse recovery current can damage the switching element. This capacitor acts as a protective buffer that absorbs the harmful reverse recovery current, preventing reverse voltage spikes from reaching the switching element
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient power factor correction in high-current applications by minimizing conduction losses and reverse voltage application, while maintaining a current critical mode operation and reducing parasitic capacitance-related currents.
Implementation Method 1
a master reactor (L1) and a slave reactor (L2) provided in the master power supply line and the slave power supply line respectively
Implementation Method 2
a first master diode (D11) and a first slave diode (D21) connected in series to the master reactor and to the slave reactor
Implementation Method 3
a master insulated gate bipolar transistor (S1) provided between a node between the master reactor and the master diode, and the low power supply line
Implementation Method 4
a second slave diode (D22) connected in parallel to the slave insulated gate bipolar transistor (S2)
Data Source
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AI summary
The present invention relates to a power factor correction circuit capable of eliminating a reverse voltage. A master transistor (S1) and a slave transistor (S2) are both insulated gate bipolar transistors. A slave diode (D21) is connected in anti-parallel to the slave transistor (S2). The master transistor (S1) is brought into conduction if a current flowing in a master reactor (L1) becomes zero, and is brought into nonconduction after elapse of a first period. The slave transistor (S2) is brought into conduction subject to elapse of a certain period after the master transistor (S1) is brought into conduction that is one of conditions for conduction of the slave transistor (S2), and is brought into nonconduction after elapse of a second period shorter than the first period. The certain period is shorter than a period from when the master transistor (S1) is brought into conduction until when the master transistor (S1) is brought into conduction again.