IGBT Proton Exposure Snapback Tradeoff
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Solution Overview
Problem
Conventional high withstand voltage power devices IGBTs face challenges in maintaining robustness and stability at low temperatures, particularly at −55° C, due to increased defect layers in n− type semiconductor substrates exposed to protons, leading to reduced minority carrier lifetime and increased snapback phenomena.
Innovation Solution
A semiconductor device structure with a p type collector layer and an n+ type buffer layer, optimized in concentration and depth, is exposed to a controlled amount of protons, combined with a donor layer to improve the low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff characteristic and prevent snapback phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the n− layer's thickness is large and the semiconductor substrate's inherent impurity concentration is small, then high withstand voltage is achieved, but a smaller transport factor is provided which increases snapback phenomenon
Solution Approach 1:
The patent introduces a localized p-type collector layer at the back surface of the semiconductor substrate, creating a non-uniform impurity distribution. This local modification improves hole injection at the back surface without affecting the overall n− layer thickness and bulk impurity concentration, thus maintaining high withstand voltage while improving transport factor to reduce snapback phenomenon.
Solution Approach 2:
The patent modifies the impurity concentration parameter by introducing a p-type collector layer with controlled doping concentration (10^16 to 10^18 atoms/cm³) at the back surface. This parameter change locally increases the hole concentration, improving the transport factor and reducing snapback phenomenon without compromising the high withstand voltage capability determined by the n− layer thickness.
2Duration of action of moving object
If the semiconductor substrate is exposed to a large quantity of protons, then lifetime control is achieved, but the defect layer increases which reduces minority carrier lifetime
Solution Approach 1:
The patent converts the harmful effect of proton exposure by introducing a p-type collector layer that benefits from the proton-induced defects. The defect layer created by proton exposure is strategically positioned within the p-type collector layer where it can be tolerated or even utilized, while the main n− layer remains protected. This allows lifetime control through proton exposure without severely degrading minority carrier lifetime in the active regions.
3Strength
If the back surface contains an impurity reduced in concentration, then high withstand voltage is achieved, but snapback phenomenon more readily occurs
Solution Approach 1:
The patent applies local quality by creating a p-type collector layer at the back surface with controlled impurity concentration. This localized impurity enrichment at the back surface improves hole injection and transport factor without affecting the overall low impurity concentration of the n− layer, thus maintaining high withstand voltage while reducing snapback phenomenon.
4Reliability
If the n− type semiconductor substrate is exposed to protons to control lifetime, then transport factor is improved, but defect layer increases which reduces minority carrier lifetime
Solution Approach 1:
The patent converts the harmful proton-induced defects into a beneficial structure by introducing a p-type collector layer where these defects are localized. The proton exposure creates defects that are confined to the p-type collector region, where they do not severely impact minority carrier lifetime in the active n− layer. This allows transport factor improvement through controlled proton exposure while managing the defect layer impact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized structure achieves a stabilized low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff characteristic, reduces variation in low saturation voltage, and enhances the robustness of IGBT modules against destruction, ensuring reliable operation across a range of temperatures.
Implementation Method 1
exposing it to protons in an optimized amount to improve low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff
Data Source
AI summary
A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 μm, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 μm. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 μm as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.