IGBT Dummy Cell P-well Segmentation for Vcesat Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing IGBT structures with deep P-well designs require additional diffusion processes, increasing process costs and resulting in high forward saturation voltage due to large area PN junctions, which reduces stored carrier density and efficiency.
Innovation Solution
A semiconductor device design with continuous P-well regions in active cells and discontinuous, electrically floating P-well regions in dummy cells, allowing simultaneous fabrication and reducing the area of PN junctions, along with the option of a polysilicon-bridge over dummy cells to act as a self-aligned mask for implant processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If deep P-well design is used in dummy cells, then gate capacitance is reduced, but process cost increases due to additional diffusion process
Solution Approach 1:
The patent applies local quality by differentiating the P-well structure between active cells and dummy cells. In active cells, continuous P-wells extend to the N- drift layer for optimal carrier storage and low Vcesat. In dummy cells, discontinuous P-wells are terminated before reaching the N- drift layer, reducing the need for additional diffusion processes while maintaining reduced gate capacitance benefits.
Solution Approach 2:
The patent segments the P-well structure into two distinct types: continuous P-wells in active cells and discontinuous P-wells in dummy cells. This segmentation allows each region to be optimized independently - active cells for low forward saturation voltage and dummy cells for reduced gate capacitance with simplified manufacturing.
2Use of energy by moving object
If deep P-well design is used in dummy cells, then gate capacitance is reduced, but forward saturation voltage increases due to large area PN junction reducing stored carrier density
Solution Approach 1:
The patent applies local quality by differentiating the P-well structure between active cells and dummy cells. In active cells, continuous P-wells extend to the N- drift layer for optimal carrier storage and low Vcesat. In dummy cells, discontinuous P-wells are terminated before reaching the N- drift layer, reducing the need for additional diffusion processes while maintaining reduced gate capacitance benefits.
Solution Approach 2:
The patent segments the P-well structure into two distinct types: continuous P-wells in active cells and discontinuous P-wells in dummy cells. This segmentation allows each region to be optimized independently - active cells for low forward saturation voltage and dummy cells for reduced gate capacitance with simplified manufacturing.
3Reliability
If continuous P-well regions are used in active cells, then stored carrier density is increased and Vcesat is reduced, but device complexity increases
Solution Approach 1:
The patent merges the P-well formation process for both active and dummy cells into a single diffusion process. By using the gate trench structure as a self-aligned mask, continuous P-wells in active cells and discontinuous P-wells in dummy cells are formed simultaneously, reducing device complexity and manufacturing steps despite the different P-well configurations.
Solution Approach 2:
The gate trench structure serves as a self-aligned mask during the diffusion process, automatically defining where continuous P-wells form (in active cells) and where discontinuous P-wells form (in dummy cells). This self-service mechanism eliminates the need for additional masking steps and reduces overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves lower forward saturation voltage and improved turnoff performance with reduced process costs, as evidenced by lower Vcesat and turnoff energy, and higher stored carrier density during forward conduction.
Implementation Method 1
a gate trench having a conductive core that is surrounded by a gate oxide layer
Implementation Method 2
a layered semiconductor material disposed on the metal collector layer being selectively doped to provide; a first P-type collector layer disposed on the metal collector layer
Implementation Method 3
one or more N+ region alternating with a plurality of P+ regions
Data Source
AI summary
A semiconductor device includes: metal collector layer on backside, P-type collector layer, N-type field stop layer and N− drift layer. There are active cells and dummy cells on top of the device. The active cell and dummy cell are separated by gate trench. The gate trench is formed by polysilicon and gate oxide layer. There are N+ region and P+ region in active cells, and they are connected to metal emitter layer through the window in the insulation layer. There are P-well regions in both active cells and dummy cells. The P-well regions in active cells are continuous and connected to emitter electrode through P+ region. The P-well regions in dummy cells are discontinuous and electrically floating.