IGBT Double Gate Driving via Resistive Layer
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Solution Overview
Problem
Existing insulated gate bipolar transistors (IGBTs) face challenges in reducing both on-resistance and switching loss, particularly during turn-off, due to delayed carrier discharge from the n-type drift region, which increases turn-off time and switching loss.
Innovation Solution
The implementation of a double gate driving technique using a resistive layer within the IGBT chip to delay the potential change of one gate electrode with respect to the other, allowing for single gate electrode pad operation without increasing chip area, thereby achieving reduced on-resistance and switching loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the carrier concentration of the n-type drift region is increased to reduce on-resistance, then on-resistance is reduced, but turn-off time increases and switching loss increases due to delayed carrier discharge
Solution Approach 1:
The gate electrode is divided into two separate gate electrodes (first gate electrode and second gate electrode), each controlling different regions of the semiconductor layer. This segmentation allows independent control of carrier injection and discharge processes, enabling the first gate to turn on the device while the second gate manages turn-off, thereby reducing turn-off time without compromising on-resistance
Solution Approach 2:
The second gate electrode is configured to discharge carriers from the n-type drift region before the first gate electrode fully turns off the device. This preliminary action of carrier discharge reduces the stored charge that would otherwise cause delayed turn-off, thereby reducing turn-off time and switching loss while maintaining low on-resistance
2Loss of energy
If double gate driving is implemented to reduce both on-resistance and switching loss, then both parameters are improved, but device complexity increases due to additional gate driving systems
Solution Approach 1:
The first and second gate electrodes are merged into a single integrated gate structure that penetrates through the semiconductor layer, sharing common insulating films and fabrication processes. This merging reduces manufacturing complexity while maintaining the functional benefits of dual gate control for reduced switching loss
Solution Approach 2:
The single gate structure serves multiple functions: the first gate electrode controls carrier injection for low on-resistance, while the second gate electrode controls carrier discharge for reduced switching loss. This multi-functionality eliminates the need for separate gate driving systems, reducing device complexity while achieving both performance goals
3Productivity
If two gate electrode pads are provided for double gate driving, then switching performance is improved, but chip area increases
Solution Approach 1:
The first and second gate electrodes are electrically connected to a single gate electrode pad through the semiconductor layer, merging the input connections. This allows both gates to be controlled from one pad location, avoiding the need for two separate pads and thereby reducing chip area while maintaining dual gate functionality for improved switching speed
Solution Approach 2:
The semiconductor layer itself acts as an intermediary medium that allows electrical connection from the single gate electrode pad to both the first and second gate electrodes. This intermediary function enables signal distribution to multiple gates without requiring multiple external connection points, thus reducing chip area while preserving switching performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces on-resistance during on-state and minimizes switching loss by utilizing the resistive layer to control gate electrode potential differences, enabling efficient double gate driving without the need for additional gate electrode pads.
Implementation Method 1
a first resistive layer provided in the third trench; a gate electrode pad provided on the side of the first plane of the semiconductor layer, the gate electrode pad being electrically connected to the first gate electrode through the first resistive layer, the gate electrode pad being electrically connected to the second gate electrode
Data Source
AI summary
A semiconductor device according to as embodiment includes a semiconductor layer having a first plane and a second plane; a first trench provided in the semiconductor layer; a first gate electrode provided in the first trench; a second trench provided in the semiconductor layer; a second gate electrode provided in the second trench; a third trench provided in the semiconductor layer; a first resistive layer provided in the third trench; a first electrode provided on a side of the first plane of the semiconductor layer; a second electrode provided on a side of the second plane of the semi conductor layer; and a gate electrode pad provided on the side of the first plane of the semiconductor layer, is electrically connected to the first gate electrode through the first resistive layer, and is electrically connected to the second gate electrode.