IGBT Ring Gate Electrode Layout for Switching Loss Reduction
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Solution Overview
Problem
The GG type structure of semiconductor devices experiences issues with displacement current generation due to potential fluctuations in the floating region, leading to deterioration in switching loss, breakdown strength, current vibrations, and voltage surges, while the GGEE type structure attempts to mitigate this by forming a parasitic p-type MOSFET, but ends up increasing input capacitance and reducing di/dt and dv/dt, thereby worsening switching loss.
Innovation Solution
The semiconductor device incorporates a GGEE type structure with ring-shaped gate electrodes separated in the first direction, reducing the facing area between active and inactive cell areas, which decreases input capacitance and enhances the injection enhancement effect, thereby improving switching loss and reducing potential fluctuations in the floating region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a GGEE type structure is used to suppress potential fluctuations in the floating region, then reliability is improved, but input capacitance increases and switching loss deteriorates
Solution Approach 1:
The gate electrode is divided into two independent gates: a first gate coupled to gate potential and a second gate coupled to emitter potential. This segmentation allows each gate to perform its specific function independently, enabling suppression of potential fluctuations in the floating region through the second gate while maintaining proper switching control through the first gate, thereby avoiding the increased input capacitance associated with conventional GGEE structures.
Solution Approach 2:
Different regions of the device are given different electrical characteristics: the first gate controls the active cell area for switching operations, while the second gate controls the inactive cell area with the floating region. This local differentiation allows the second gate to suppress potential fluctuations locally in the floating region without affecting the overall input capacitance of the device.
2Loss of energy
If trench gates are narrowed and separated to reduce input capacitance, then switching loss is improved, but the ability to suppress potential fluctuations in the floating region is reduced
Solution Approach 1:
The gate structure is segmented into two independent gates with different functions. The first gate (trench gate) can be narrowed and separated to reduce input capacitance and improve switching loss, while the second gate (ring gate or additional trench gate) is specifically positioned to control the floating region and suppress potential fluctuations, compensating for the reduced suppression capability caused by the narrowed first gate.
Solution Approach 2:
The second gate acts as an intermediary element that specifically targets the floating region to suppress potential fluctuations. This intermediary gate compensates for the reduced suppression capability caused by narrowing and separating the first trench gates, allowing both objectives to be achieved simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces input capacitance, suppresses potential fluctuations, and enhances switching performance by optimizing the layout of gate electrodes and hole discharge cell areas, leading to improved switching loss and reduced off-surge voltage in load short-circuit tests.
Implementation Method 1
a GGEE type structure is provided which forms a parasitic p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) by a trench gate coupled to an emitter potential and discharges holes by the parasitic p-type MOSFET
Implementation Method 2
The IE effect is intended to make positive holes harder to be discharged from the emitter potential electrode side when the IGBT is in an on state, to thereby enhance the concentration of an electric charge accumulated in a drift region
Data Source
AI summary
To enhance the performance of a semiconductor device. Gate electrodes extending in a Y direction and applied with a gate potential, and emitter regions and base regions both applied with an emitter potential are formed in an active cell area. The plural emitter regions are formed so as to be separated from each other in the Y direction by the base regions. A plurality of hole discharge cell areas having a ring-shaped gate electrode applied with an emitter potential are formed within an inactive cell area. The hole discharge cell areas are arranged to be separated from each other along the Y direction. Thus, an input capacitance of an IGBT is reduced, and a switching loss at turn on of the IGBT is improved.