IGBT Sense Current Surge Suppression via Local Quality
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Solution Overview
Problem
Existing semiconductor devices face complexity in manufacturing processes and surges in sense current due to structural differences between main and sense IGBT cells, leading to erroneous overcurrent protection.
Innovation Solution
A semiconductor device with a single-crystalline structure featuring first and second semiconductor element portions, where the second portion has a thicker gate insulating film to delay turn-on and prevent current concentration, utilizing the difference in chemical combination reaction rates based on plane orientation to simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the voltage threshold value of sense IGBT cells is set higher than main IGBT cells to delay turn-on and suppress sense current surge, then the sense current surge is suppressed, but the manufacturing process becomes complicated with increased photolithography steps
Solution Approach 1:
The patent applies local quality by forming a gate insulating film with different thicknesses in different regions: a first thickness in the main IGBT cell region and a second thickness (greater than the first) in the sense IGBT cell region. This local differentiation of the gate insulating film thickness directly creates the voltage threshold difference between main and sense cells, suppressing sense current surge during turn-on without requiring additional photolithography steps or process complexity.
2Manufacturing precision
If additional photolithography steps are performed to create different gate insulating film thicknesses, then voltage threshold differentiation is achieved, but manufacturing time and process complexity increase
Solution Approach 1:
The patent merges the formation of different thickness gate insulating films into a single chemical vapor deposition (CVD) process step. By controlling deposition conditions such as temperature gradients or gas flow distribution during one CVD process, the gate insulating film is formed with varying thicknesses across different regions simultaneously, achieving voltage threshold differentiation without requiring multiple separate photolithography and deposition cycles.
Solution Approach 2:
The patent utilizes parameter changes during the CVD process to achieve different gate insulating film thicknesses. By varying process parameters such as temperature, pressure, or gas flow rate in different spatial regions during deposition, the film thickness is controlled to be greater in the sense IGBT cell region than in the main IGBT cell region,从而实现 voltage threshold differentiation in a single process step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses surges in sense current, reduces manufacturing complexity, and enhances the reliability of overcurrent protection by ensuring accurate voltage threshold differences between main and sense current components.
Implementation Method 1
First and second gate insulating films covering the first and second channel surfaces, respectively, are formed by chemical combination reaction on the first and second channel surfaces
Data Source
AI summary
A first semiconductor element portion for switching a first current includes a first channel surface having a first plane orientation. A first region of a semiconductor layer includes a first trench having the first channel surface. A first gate insulating film covers the first channel surface with a first thickness. A second semiconductor element portion for switching a second current smaller than the first current includes a second channel surface having a second plane orientation different from the first plane orientation. A second region of the semiconductor layer includes a second trench having the second channel surface. A second gate insulating film covers the second channel surface with a second thickness larger than the first thickness.