IGBT Current Sensor Trench Drainage for Latch-up Prevention
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Solution Overview
Problem
In power semiconductors, particularly insulated gate bipolar transistors (IGBTs), there is a risk of latch-up and cell overloading due to charge carrier plasma accumulation in cell-free areas, especially at the edges of the sensor and main emitter areas, which can lead to short-circuit or overload conditions.
Innovation Solution
A circuit arrangement is implemented where the emitter terminals of IGBT cells are connected to both an output terminal and a sensor connection via separate conductive layers, with a trench structure and doped layer draining holes away from main cells, allowing the sensor cells to be embedded closely while preventing overload on adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the sensor connection is incompletely filled with emitter cells to allow independent design of sensor area, then the sensor area can be designed independently of the main emitter area, but cell-free areas are created where charge carrier plasma builds up causing latch-up risk
Solution Approach 1:
The patent divides the emitter area into two distinct segments: main emitter cells and sensor emitter cells. This segmentation allows the sensor area to be independently designed and sized according to measurement requirements while maintaining a controlled transition zone. The trench structure further segments the cell-free area, isolating the plasma buildup region from the main emitter cells.
Solution Approach 2:
The patent introduces a trench structure as an intermediary element between the sensor cells and main emitter cells. This trench creates a controlled intermediate zone that manages the transition between the two cell types and provides a designated area for charge carrier plasma to dissipate without directly impacting the main emitter cells.
2Reliability
If the sensor connection is completely filled with emitter cells to eliminate cell-free areas, then latch-up risk is reduced, but the sensor area cannot be independently designed and the embedding is very tight
Solution Approach 1:
The patent applies different structural qualities to different regions: the sensor area uses a completely filled connection with tight embedding for reliability, while the main emitter area maintains its standard structure. The trench structure introduces a localized modification that allows plasma management without compromising the independent design capability of the sensor region.
3Productivity
If the sensor cells are closely embedded in the main emitter to maximize space utilization, then manufacturing efficiency is improved, but the load on bordering cells from charge carrier plasma increases
Solution Approach 1:
The patent extracts the problematic cell-free area and plasma buildup region from the immediate vicinity of the main emitter cells by positioning the sensor connection at the edge of the semiconductor substrate. This extraction removes the source of harmful plasma effects while maintaining close embedding of sensor cells for space efficiency.
Solution Approach 2:
The patent relocates the sensor connection to the edge region of the substrate, utilizing the peripheral dimension rather than embedding sensor cells within the central emitter area. This dimensional repositioning allows close embedding without the harmful plasma interaction that would occur with central placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the load on main cells from charge carrier plasma, enabling independent design of the sensor area and preventing latch-up events, thus enhancing the reliability of the power semiconductor chip.
Implementation Method 1
a doped layer connected to the first conductive layer and which also extends between the transistor cells of the first area and the transistor cells of the second region. The doped layer is arranged below the sensor connection. According to the invention, the emitter consisting of the IGBT cells is divided into two cell groups. The doped region connected to the first conductive layer is used to drain off the holes that flow out during the turn-off process
Data Source
AI summary
The invention relates to a semiconductor arrangement for a current sensor in a power semiconductor, which arrangement comprises, on a substrate (1), a multiple arrangement of transistor cells (2) with an insulated gate electrode, the emitter connections (10) of which in a first region (12) are connected to at least one output connection (25) via a first conductive layer (16) and the emitter connections (10) of which in a second region (13) are connected to at least one sensor connection (18) via a second conductive layer (17), which sensor connection is arranged outside a first cell region boundary (14) which surrounds the transistor cells (2) of the first region (12) and the transistor cells (2) of the second region (13), wherein a trench structure belonging to the first cell region boundary (14) is formed between the transistor cells (2) of the second region (13) and the sensor connection (18) and is adjoined, in the direction of an outer edge of the substrate (1), by a doped layer (15) connected to the first conductive layer (16).