IGBT Silicon Wafer COP Reduction via Annealing
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Solution Overview
Problem
Silicon wafers produced by the Czochralski method (CZ method) for insulated gate bipolar transistors (IGBTs) face issues with gate oxide integrity, resistivity fluctuations, recombination lifetime deterioration, and the presence of crystal-originated particles (COPs), which hinder their suitability as substrates due to high oxygen concentrations and impurity segregation.
Innovation Solution
A method involving the growth of silicon ingots with low interstitial oxygen concentrations, neutron irradiation for homogeneous phosphorus doping, and annealing in an oxidizing atmosphere to form a silicon oxide layer that fills COPs, along with nitrogen doping to reduce COP sizes and inhibit slip dislocations, and forming a strained layer as a gettering layer to remove heavy metals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If silicon wafers are produced by the CZ method to achieve large diameter and mass production, then productivity and ease of manufacture are improved, but crystal-originated particles (COPs) are generated that deteriorate gate oxide integrity
Solution Approach 1:
The patent applies preliminary action by performing heat treatment on the silicon wafer before oxide film formation to eliminate COPs. The heat treatment process is conducted in advance to prevent COPs from being captured in the oxide film layer during subsequent thermal oxidation, thereby maintaining gate oxide integrity while preserving the productivity benefits of CZ method mass production
2Reliability
If oxygen concentration in CZ silicon is controlled to eliminate COPs, then gate oxide integrity is improved, but recombination lifetime deteriorates due to oxide precipitation
Solution Approach 1:
The patent applies parameter changes by precisely controlling the oxygen concentration parameter to a specific range (1×10^18 to 5×10^18 atoms/cm³) and adjusting the heat treatment temperature parameter (900°C to 1200°C) to achieve the optimal balance. This parameter optimization eliminates COPs while preventing excessive oxide precipitation that would deteriorate recombination lifetime, thus resolving the contradiction between gate oxide integrity and carrier lifetime
3Manufacturing precision
If phosphorus doping is used to control resistivity in CZ silicon, then electrical properties are improved, but resistivity becomes non-uniform due to segregation
Solution Approach 1:
The patent applies feedback by implementing a two-stage doping strategy where phosphorus is added during crystal growth and additional phosphorus is introduced through heat treatment. The process monitors and adjusts doping levels to compensate for segregation effects, ensuring uniform resistivity distribution while maintaining precise electrical property control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in silicon wafers with reduced COPs, stable resistivity, and improved recombination lifetime, making them suitable for IGBT applications by enhancing gate oxide integrity and reducing thermal donor generation.
Implementation Method 1
annealing of the wafer in an oxidizing atmosphere, thereby forming a silicon oxide layer on a surface of the silicon wafer
Implementation Method 2
it is possible to transform a predetermined amount of the silicon atoms into phosphorus atoms by irradiating neutrons to the silicon ingot
Implementation Method 3
forming a strained layer as a gettering layer to remove heavy metals
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3D
AI summary
A silicon wafer for an IGBT is produced by forming an ingot having an interstitial oxygen concentration [Oi] of not more than 7.0 × 1017atoms/cm3 by the Czochralski method; doping phosphorus in the ingot by neutron beam irradiation to the ingot; slicing a wafer from the ingot; performing annealing of the wafer in an oxidizing atmosphere containing at least oxygen at a temperature satisfying a predetermined formula; and forming a polysilicon layer or a strained layer on one side of the wafer.