Trench IGBT Stray Capacitance Reduction via Segmented Floating Regions
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Solution Overview
Problem
Conventional trench-type IGBTs suffer from high stray capacitance between the gate junction trench and p-type floating region, leading to operating noise and on-operation loss during switching, making it difficult to achieve low-noise and low-loss characteristics while maintaining withstand voltage.
Innovation Solution
The semiconductor device design includes gate trenches filled with a gate electrode, an n+-type emitter region, a p-type base region, and an n−-type drift region, with an emitter trench formed between gate trenches at an interval of 2 μm or less, preventing stray capacitance between the gate junction trench and p-type floating region, and grounding the n−-type drift region with the p+-type collector region to stabilize capacitance changes during switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a p-type floating region is formed in a diffused manner in a drift layer to contact a gate junction trench, then the trench-type IGBT achieves high saturation voltage and short-circuit capacity, but high stray capacitance occurs in the junction region between the gate junction trench and p-type floating region, causing operating noise and on-operation loss
Solution Approach 1:
The invention divides the p-type floating region into multiple separate regions that are spaced apart from each other, rather than forming a continuous diffused region. This segmentation reduces the total junction area between the p-type floating region and the gate junction trench, thereby reducing stray capacitance and associated energy loss while maintaining the necessary electrical characteristics for high saturation voltage and short-circuit capacity.
2Area of stationary object
If the gate junction trench and p-type floating region are positioned close together, then device area is reduced, but stray capacitance increases causing noise and switching loss
Solution Approach 1:
The invention introduces an insulating film as an intermediary layer between the gate junction trench and the p-type floating region. This insulating film acts as a mediator that reduces the electrical coupling and stray capacitance between these two structures, thereby reducing noise and switching loss while allowing the structures to remain in close proximity for compact device area.
3Object-generated harmful factors
If the p-type floating region is removed to reduce stray capacitance, then noise and switching loss are reduced, but withstand voltage capability deteriorates
Solution Approach 1:
The invention applies local quality by creating discrete p-type floating regions with specific spatial distribution and dimensions rather than a uniform continuous region. The regions are positioned and sized to provide localized electrical characteristics that maintain withstand voltage capability in critical areas while minimizing stray capacitance in other areas, achieving both low noise and high reliability.
Data Source
AI summary
A semiconductor device of the present invention includes a semiconductor layer, a plurality of gate trenches formed in the semiconductor layer, a gate electrode filled via a gate insulating film in the plurality of gate trenches, an n+-type emitter region, a p-type base region, and an n−-type drift region disposed, lateral to each gate trench, in order in a depth direction of the gate trench from a front surface side of the semiconductor layer, a p+-type collector region disposed on a back surface side of the semiconductor layer with respect to the n−-type drift region, an emitter trench formed between the plurality of gate trenches adjacent to each other, and a buried electrode filled via an insulating film in the emitter trench, and electrically connected with the n+-type emitter region, and the emitter trench is disposed at an interval of 2 μm or less via an n−-type drift region with the gate trench.