IGBT Trench Emitter Layout for Saturation Current Suppression
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Solution Overview
Problem
The existing insulated-gate bipolar transistor (IGBT) devices face challenges in preventing an increase in saturation current while maintaining the Vce(sat)-Eoff trade-off characteristic and avoiding operational complexity in gate driver management.
Innovation Solution
The semiconductor device incorporates a specific trench structure with varying impurity concentrations and layer configurations, including a semiconductor substrate with selectively formed impurity layers and trenches, connected by oxide-film-encased electrode layers, to control electron injection and reduce saturation current without altering gate voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the spacing between adjacent N+ type emitter layers is increased to lower electron injection efficiency and suppress saturation current, then saturation current is reduced, but parasitic resistance in the P+ type emitter layer region increases causing deterioration in Vce(sat)-Eoff trade-off characteristic
Solution Approach 1:
The patent applies local quality by creating different impurity concentration regions within the P type layer. Specifically, a first P type layer with lower impurity concentration is formed adjacent to the gate trench, while a second P type layer with higher impurity concentration is formed in the region between N+ type emitter layers. This local differentiation allows the region near the gate trench to have lower parasitic resistance for better Vce(sat) characteristics, while the region between emitter layers has higher impurity concentration to reduce electron injection and suppress saturation current.
2Loss of energy
If the other gate electrode is driven at a lower voltage than the gate electrode to reduce electron injection and lower saturation current, then saturation current is reduced, but the operation of the gate driver becomes more complex
Solution Approach 1:
The patent applies parameter changes by modifying the impurity concentration distribution in the P type layer rather than changing the gate driving voltage. By adjusting the impurity concentration parameters of the P type layer (creating regions with different concentrations), the device achieves reduced saturation current through material property modification rather than through complex voltage control mechanisms, thereby maintaining simple gate driver operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces saturation current and improves the Vce(sat)-Eoff trade-off characteristic, ensuring short-circuit tolerance and simplifying gate driver operations.
Implementation Method 1
electrons are injected into the substrate from the gate trench and the other gate trench
Implementation Method 2
an impurity concentration of the first semiconductor layer is higher than an impurity concentration of the semiconductor substrate. An impurity concentration of the second impurity layer is higher than an impurity concentration of the first impurity layer. An impurity concentration of the third impurity layer is higher than an impurity concentration of the second impurity layer.
Data Source
AI summary
A semiconductor device includes: a first trench provided from the upper surface of a first impurity layer to the inside of a first semiconductor layer, a second trench provided from the upper surface of a second impurity layer to a position lower than the lower surface of the first semiconductor layer; a second semiconductor layer of a first conductivity type provided on the surface layer of the first impurity layer and disposed to be interposed between the first trench and a third impurity layer in a plan view; and a third semiconductor layer of the first conductivity type provided in the surface layer of the second impurity layer and disposed to be interposed between the second trench and the third impurity layer in the plan view.