Trench Gate IGBT dv/dt Control via Floating P-Layer Removal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The controllability of the time change of output voltage (dv/dt) in IGBTs and opposite-arm diodes is reduced during turn-on operations due to transient hole flow into the floating p-layer, leading to uncontrollable switching speed and increased switching loss, while attempts to improve controllability often compromise low loss and high breakdown voltage.
Innovation Solution
A semiconductor device with a trench structure where the gate electrode is divided by an insulating layer and the emitter electrode protrudes into the trench, reducing parasitic capacitance and eliminating the floating p-layer, allowing for controlled dv/dt through the gate drive circuit while maintaining low loss and high breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a floating p-layer is formed between trench gates to reduce on-state voltage and improve ruggedness, then conduction loss is reduced and device robustness is improved, but dv/dt controllability deteriorates due to transient hole flow causing gate potential rise
Solution Approach 1:
The invention extracts and removes the floating p-layer from the IGBT structure. By eliminating this layer, the patent prevents transient hole flow into the floating region during turn-on, thereby removing the source of gate potential rise and improving dv/dt controllability while maintaining low conduction loss through optimized trench gate design
Solution Approach 2:
The invention introduces an insulating layer as an intermediary between the p-collector layer and the n-emitter layer in the trench region. This insulating layer acts as a mediator that prevents direct hole flow while allowing the structure to maintain its electrical functions, thus resolving the contradiction between low conduction loss and dv/dt controllability
2Ease of operation
If gate resistance is increased to control dv/dt during turn-on, then switching speed is reduced and switching loss increases, but dv/dt controllability is improved
Solution Approach 1:
By removing the floating p-layer, the invention eliminates the mechanism that causes gate potential rise during turn-on. This allows the use of lower gate resistance values to achieve both dv/dt controllability and fast switching speed, thereby reducing switching loss while maintaining ease of operation
3Strength
If trench gate interval is widened to reduce electric field and improve breakdown voltage, then device ruggedness is improved, but current flow area is reduced increasing conduction loss
Solution Approach 1:
The invention applies different properties to different regions: the trench gate structure provides high breakdown voltage through controlled electric field distribution in the widened interval regions, while the n-emitter layer with high carrier concentration in the current flow regions maintains low conduction loss. This local differentiation resolves the contradiction between strength and energy loss
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces reverse transfer capacitance, enhancing dv/dt controllability during turn-on switching times while maintaining low loss and high breakdown voltage, as demonstrated by simulated collector voltage dependencies and waveform control.
Implementation Method 1
reducing parasitic capacitance and eliminating the floating p-layer, allowing for controlled dv/dt through the gate drive circuit
Implementation Method 2
there is also an advantage that an electric field applied to the trench gate is relaxed by a p-n junction formed of the floating p-layer 105 and an n -
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device provides a gate electrode (401) formed on a lateral face of a wide trench (423), and thereby cover the gate electrode is covered by a gate insulating layer (402) and a thick insulating layer (403) to be an inter layer. Therefore, a parasitic capacitance of the gate becomes small, and there is no potential variation of the gate since there is no floating p-layer so that a controllability of the dv/dt can be improved. In addition, the conductive layer between the gate electrodes can relax the electric field applied to the corner of the gate electrode. In consequence, compatibility of low loss and low noise can be achieved.