IGBT Gate Trench Resistor Layout for Oxide Insulation Reliability
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Solution Overview
Problem
In semiconductor devices with IGBTs, defects in the p-type collector region can lead to insulation breakdown in the silicon oxide film under the resistive element connected to the gate pad, reducing the reliability of the device.
Innovation Solution
The semiconductor device incorporates a trench formed in the p-type well region with a resistive element filled through a thin silicon oxide film, similar to the gate insulating film, which increases parasitic resistance and reduces the likelihood of insulation breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trench is formed in the p-type well region with a thin silicon oxide film (same thickness as gate insulating film), then the parasitic resistance of the p-type well region increases, but the insulation breakdown of the silicon oxide film becomes more likely due to high potential rise
Solution Approach 1:
The p-type well region is segmented into multiple regions by forming trenches that divide it into several isolated p-type well regions. This segmentation increases the parasitic resistance of the p-type well region, which helps to reduce the potential rise caused by impact ionization and improves the reliability of the silicon oxide film insulation.
Solution Approach 2:
The silicon oxide film thickness is optimized locally: it is thin (same as gate insulating film) in the trench to increase parasitic resistance, but the trench structure itself provides the necessary electrical isolation. This local quality adjustment allows the system to achieve both high parasitic resistance and adequate insulation reliability.
2Ease of manufacture
If the silicon oxide film thickness is reduced to match the gate insulating film thickness, then manufacturing complexity is reduced, but insulation breakdown becomes more likely due to increased parasitic resistance and potential rise
Solution Approach 1:
The p-type well region is divided into multiple isolated regions by trenches, which increases the overall parasitic resistance. This allows the use of thinner silicon oxide film (matching gate insulating film thickness) without compromising insulation reliability, as the segmented structure compensates for the reduced film thickness by providing multiple isolation paths.
Solution Approach 2:
The patent changes the structural parameter of the p-type well region from a continuous structure to a segmented structure with trenches. This parameter change increases the effective parasitic resistance, allowing the silicon oxide film thickness to be reduced to match the gate insulating film thickness while maintaining adequate insulation reliability.
3Reliability
If the parasitic resistance of the p-type well region is increased to reduce potential rise, then insulation reliability improves, but the device complexity increases due to additional trench structures
Solution Approach 1:
The patent merges the function of increasing parasitic resistance with the existing trench structure used for other device functions. The trenches that are already present in the device structure are utilized to segment the p-type well region, thereby increasing parasitic resistance without adding entirely new structural elements. This merging approach improves insulation reliability while minimizing the increase in device complexity.
Solution Approach 2:
The trench structure serves multiple functions: it segments the p-type well region to increase parasitic resistance, provides physical isolation between different regions, and maintains compatibility with the existing device architecture. This multi-functionality allows the patent to improve insulation reliability without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of the semiconductor device by reducing potential rises in the p-type well region and preventing insulation breakdown, thus maintaining device performance and longevity.
Implementation Method 1
a resistive element formed in an endless shape in plan view and filled through an insulating film
Implementation Method 2
a third contact member located between the first and second contact members in the first direction in plan view, located in an area surrounded by the inner circumference of the resistive element, and connected to the well region
Data Source
AI summary
Improve the reliability of a semiconductor device. A resistive element Rg is filled in a trench TR formed in a well region PW of a semiconductor substrate. The resistive element Rg and the trench TR have an endless shape in plan view. The resistive element Rg is connected to a first contact member PG that is electrically connected to a gate pad GP, and a second contact member PG that is electrically connected to a gate wiring GW. Furthermore, a third contact member PG, which electrically connects an emitter electrode EE to the well region PW, is positioned in an area surrounded by an endless shape of the resistive element Rg, between the first and second contact members PG in a Y direction.