IGFET Empty-Well Retrograde Doping for Threshold Stability
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Solution Overview
Problem
Current semiconductor technologies face challenges in achieving high-performance Insulated-Gate Field-Effect Transistors (IGFETs) for both digital and analog applications, particularly in maintaining low parasitic capacitances and threshold voltage stability as device dimensions shrink, leading to issues with punchthrough and hot carrier injection.
Innovation Solution
The development of a semiconductor fabrication platform utilizing a combination of empty-well and filled-well regions in IGFETs, where empty-well regions have a reduced dopant concentration near the surface and filled-well regions have increased dopant concentration near the surface, allowing for symmetric and asymmetric IGFET designs that reduce parasitic capacitances and stabilize threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is reduced to increase productivity and decrease device size, then the IGFET operates in the short-channel regime with improved integration density, but punchthrough occurs and threshold voltage control is lost
Solution Approach 1:
The patent applies local quality by creating a retrograde well with non-uniform dopant distribution - heavily doped at subsurface depths and lightly doped near the surface. This localized doping strategy provides punchthrough prevention exactly where needed (at the source-drain junction depths) while maintaining short channel length for high integration density.
Solution Approach 2:
The patent transitions from two-dimensional planar doping to three-dimensional vertical doping profiles by implementing retrograde wells with maximum dopant concentration at subsurface depths rather than at the surface. This vertical dimension allows simultaneous achievement of short channel length and punchthrough prevention.
2Reliability
If the dopant concentration is increased in the channel zone to prevent punchthrough, then surface punchthrough is inhibited, but hot carrier injection into the gate dielectric layer increases
Solution Approach 1:
The retrograde well structure provides high dopant concentration locally at the source-drain junction depths to prevent punchthrough, while maintaining lower dopant concentration in the channel zone near the surface where hot carrier injection would occur. This spatially selective doping resolves the contradiction between punchthrough prevention and hot carrier injection reduction.
3Reliability
If a filled-well structure is used to stabilize threshold voltage, then threshold voltage control is improved, but parasitic capacitances increase
Solution Approach 1:
The retrograde well provides threshold voltage stabilization through subsurface doping while minimizing parasitic capacitance by keeping the dopant concentration low near the surface where the gate electrode is located. The capacitive effect is reduced because the high-dopant region is positioned at greater depths away from the gate.
Solution Approach 2:
The patent uses vertical positioning of dopant concentration to decouple threshold voltage control from parasitic capacitance effects. By placing the maximum dopant concentration at subsurface depths rather than at the surface, the well stabilizes threshold voltage while minimizing capacitive coupling with the gate electrode.
4Reliability
If the IGFET is designed as symmetric with two-part source and drain, then performance is improved, but device complexity increases
Solution Approach 1:
The retrograde well structure serves multiple functions simultaneously: it prevents punchthrough, stabilizes threshold voltage, and reduces parasitic capacitances. This universal structure replaces the need for complex symmetric source-drain configurations, simplifying the overall device design while maintaining high performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of high-performance IGFETs with reduced parasitic capacitances, improved switching speed, and stable threshold voltages, suitable for both digital and analog applications, enhancing the versatility of the semiconductor platform.
Implementation Method 1
a gate dielectric layer electrically insulates a gate electrode from a channel zone
Implementation Method 2
introducing a dopant of a first conductivity type into a body material of a semiconductor body
Implementation Method 3
The concentration of the dopant of the first conductivity type (i) locally reaches a subsurface concentration maximum
Data Source
Figure 1~2
Figure 3a~6
Figure 7a~8b
AI summary
Insulated-gate field-effect transistors ("IGFETs"), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (100, 102, 112, 114, 124, or 126) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (180, 182, 192, 194, 204, or 206). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (240, 242, 280, 282, 520, 522, 550, 552, 720, 722, 752, or 752) has a main portion (240M, 242M, 280M, 282M, 520M, 522M, 550M, 552M, 720M, 722M, 752M, or 752M) and a more lightly doped lateral extension (240E, 242E, 280E, 282E, 520E, 522E, 550E, 552E, 720E, 722E, 752E, or 752E). Alternatively or additionally, a more heavily doped pocket portion (250 or 290) of the body material extends along one of the source/drain zones. When present, the pocket portion typically causes the IGFET to be an asymmetric device.