IGFET Shield Electrode Structure Using Self-Aligned Spacers
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Solution Overview
Problem
The semiconductor industry faces challenges in forming insulated gate field effect transistor (IGFET) devices with tight geometries due to complex process steps and thick oxidation layers, which hinder manufacturability, performance, and reliability.
Innovation Solution
A scalable, self-aligned method is developed using a disposable dielectric layer to form dielectric plugs and spacers, enabling shallower trench structures, thinner epitaxial layers, and gate silicide enhancement regions, allowing for smaller geometry configurations without expensive capital investments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thick oxidation layers are used to form self-aligned source and body contacts, then alignment precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent removes the thick oxidation layer requirement by extracting the self-alignment function from oxidation-based processes and replacing it with a spacer-based alignment system. The spacer structure provides the necessary alignment without requiring thick oxidation layers, thereby simplifying the overall process while maintaining precision.
Solution Approach 2:
The patent changes the critical parameter from oxidation layer thickness to spacer dimensions. By controlling spacer width through deposition and etching parameters rather than oxidation parameters, the process achieves self-alignment with reduced complexity and without requiring thick oxidation layers.
2Manufacturing precision
If thick oxidation layers are used for self-aligned contacts, then alignment is improved, but manufacturing time and cost increase
Solution Approach 1:
The patent extracts the time-consuming thick oxidation step from the process sequence and replaces it with faster spacer formation techniques. The spacer can be formed through controlled deposition and pattern transfer, which are generally faster than growing thick oxidation layers, thereby reducing manufacturing time while maintaining alignment precision.
3Strength
If deeper trenches and thicker epitaxial layers are used, then blocking voltage performance is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent performs preliminary action by forming the spacer structure early in the process, which then serves as a template for subsequent trench formation. This allows the trench depth and epitaxial layer thickness to be optimized for blocking voltage performance without requiring additional complex process steps, as the spacer already defines the critical dimensions.
4Reliability
If tighter geometries are implemented, then device performance is improved, but manufacturing difficulty increases
Solution Approach 1:
The patent implements self-service through the spacer structure, which automatically defines the geometry of subsequent features through self-aligned etching. The spacer width directly determines trench width and other critical dimensions without requiring additional alignment steps, enabling tighter geometries to be manufactured with the same or reduced complexity.
Data Source
AI summary
A method for forming a transistor having insulated gate electrodes and insulated shield electrodes within trench regions includes forming dielectric stack overlying a substrate. The dielectric stack includes a first layer of one material overlying the substrate and a second layer of a different material overlying the first layer. Trench regions are formed adjacent to the dielectric stack. After the insulated shield electrodes are formed, the method includes removing the second layer and then forming the insulated gate electrodes. Portions of gate electrode material are removed to form first recessed regions, and spacers are formed within the first recessed regions. Enhancements regions are then formed in the gate electrode material self-aligned to the spacers.