IGTO Device With Segmented Gates For Low Capacitance
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Solution Overview
Problem
Insulated gate turn-off devices (IGTOs) have high capacitance and saturation current, which affect switching speed and power dissipation, and existing structures do not allow for customizable input capacitance and saturation current without increasing ON voltage or adding fabrication steps.
Innovation Solution
Modifying the IGTO structure by increasing the pitch between gates, forming separated gates within the gate mesh, and creating passive cells with no source regions or floating gates to reduce capacitance and saturation current, while maintaining low ON voltage and customizable parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the gate mesh structure with thin gate oxide is used, then the device can achieve low ON voltage and high current density, but the capacitance between gate and source/body becomes relatively high
Solution Approach 1:
The gate mesh is segmented into active gate regions and passive gate regions. The passive gate regions have their gate oxide thickness increased, reducing capacitance without affecting the active regions that maintain low ON voltage. This segmentation allows simultaneous optimization of both switching speed and power characteristics.
Solution Approach 2:
Different regions of the gate structure are assigned different gate oxide thicknesses. The active cell regions maintain thin gate oxide for low ON voltage, while the passive gate regions use thicker gate oxide to reduce capacitance. This local differentiation resolves the contradiction between low ON voltage and fast switching.
2Productivity
If the gate mesh structure with large plate area is used, then the device can conduct high current, but the capacitance between gate and source/body increases
Solution Approach 1:
The gate structure is divided into active gate areas that conduct current and passive gate areas that primarily provide isolation. The passive areas have reduced plate area or increased gate oxide thickness, reducing total capacitance while active areas maintain the geometry needed for high current conduction.
Solution Approach 2:
Passive gate regions are extracted from the continuous gate mesh structure. These passive regions are separated and configured with different parameters (thicker gate oxide, reduced area) to reduce capacitance without removing the essential current-conducting active gate regions.
3Speed
If the IGTO structure is modified to reduce capacitance by increasing gate pitch, then switching speed improves, but the device area increases
Solution Approach 1:
Instead of uniformly increasing gate pitch across the entire device, the invention applies local modifications only to passive gate regions. The active gate regions maintain their original pitch and dimensions for optimal current conduction, while passive regions are spaced further apart or have reduced dimensions, reducing capacitance without significantly increasing overall device area.
4Area of stationary object
If the gate mesh density is increased to reduce device area, then the device occupies less space, but the capacitance and saturation current increase
Solution Approach 1:
The gate mesh is segmented into active and passive regions. The passive regions, which contribute to saturation current, are configured with thicker gate oxide or reduced area, reducing their harmful effect. The active regions maintain high density for area efficiency while contributing to useful current conduction.
Solution Approach 2:
The gate oxide thickness parameter is changed specifically in passive gate regions to reduce saturation current. By increasing the gate oxide thickness in passive regions, the electric field control is reduced, thereby lowering the saturation current contribution from these regions while maintaining the compact high-density structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modified IGTO structure achieves lower capacitance and saturation current, enabling faster switching and self-limiting current, with customizable input capacitance and saturation current without increasing ON voltage or affecting other parameters.
Implementation Method 1
A gate electrode 22 is used to bias the vertical gates 12. When the gates 12 are suitably positively biased, the effective base width of the vertical NPN transistor is reduced, increasing its beta
Implementation Method 2
The capacitance between the gate (at one voltage) and the adjacent N+ source/P-body (at another voltage) is relatively high since the gate and source/body are separated by a thin gate oxide
Data Source
AI summary
An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N− epi layer, a P-well, vertical insulated gates formed in the P-well, and N+ regions between at least some of the gates, so that vertical NPN and PNP transistors are formed. A source/emitter electrode is on top, and a drain/cathode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the source/emitter electrode. Some of the cells are passive, having gates that are either not connected to the active gates or having gates that are shorted to their associated N+ regions, to customize the input capacitance and lower the saturation current. Other techniques are described to form the passive cells.