Top-Gate IGZO Array Substrate Layout for Fewer Masks and Smaller TFTs
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Solution Overview
Problem
Conventional display panels using top gate indium gallium zinc oxide thin film transistors (Top gate IGZO TFTs) require a higher number of masks, increasing costs and preventing pixel density improvement due to the need for via holes on both sides of the gate insulation layer to connect electrodes.
Innovation Solution
An array substrate design with a conductive layer having a gate electrode and drain electrode separated by insulation parts, allowing self-alignment and reducing the number of masks by reusing the second conductor part as a source electrode, thus minimizing transistor size and increasing pixel density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via holes are opened on both sides of the gate insulation layer to electrically connect the source electrode and drain electrode with the corresponding conductor-activated layer, then electrical connection is achieved, but the size of the thin film transistor increases and pixel density cannot be improved
Solution Approach 1:
The patent extracts the gate insulation layer into separate first and second insulation parts, positioning the second insulation part at the end of the active layer where via holes are already present. This allows the drain electrode to connect to the conductor-activated layer through existing via holes without requiring additional connection structures, thereby reducing transistor size while maintaining electrical connection reliability
Solution Approach 2:
The patent positions the second insulation part at the end of the active layer in the lateral dimension, allowing the drain electrode to make contact through the side of the active layer rather than requiring vertical via holes through the gate insulation layer. This dimensional repositioning eliminates the need for additional via holes while maintaining electrical connection
2Ease of manufacture
If the gate electrode, source electrode, and drain electrode layers are formed using the same metal layer, then the number of masks is reduced, but via holes must be opened on both sides of the gate insulation layer increasing transistor size
Solution Approach 1:
The gate insulation layer is extracted and divided into first and second insulation parts, with the second part positioned at the end of the active layer. This allows the drain electrode to connect through existing via holes in the second insulation part, eliminating the need for additional via holes on both sides while maintaining the single metal layer formation process
Solution Approach 2:
The second insulation part is positioned to utilize the existing via holes that are already formed in the gate insulation layer during the standard manufacturing process. This self-service approach allows the drain electrode to make electrical connection through the side of the active layer without requiring additional processing steps or extra via holes, thereby reducing transistor size while maintaining ease of manufacture
Data Source
AI summary
The present application provides an array substrate, a manufacturing method thereof, and a display panel thereof. The array substrate includes an underlay substrate, an active layer, a gate insulation layer, a conductive layer, and a first electrode. The active layer includes a channel part, a first conductor part, and a second conductor part. The conductive layer includes a gate electrode and a drain electrode. An orthographic projection of the gate electrode on the active layer is located in the channel part. The drain electrode overlaps a part of the first conductor part. The first electrode is connected to the second conductor part. Along a direction from the first conductor part to the second conductor part, the first conductor part includes a first length, the second conductor part includes a second length, and the first length is greater than the second length.