IGZO Display Panel Half-Tone Mask Single Etch Process
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Solution Overview
Problem
The existing display panel manufacturing processes require multiple masks, leading to increased costs and reduced efficiency due to complex mask processes, particularly in forming the gate, source, and drain layers in IGZO-based liquid crystal displays.
Innovation Solution
A display panel preparation method that uses a half-tone mask to form a gate insulating layer with specific thickness and hollow parts, allowing for the simultaneous etching of the gate, source, and drain layers using a single mask process, thereby reducing the number of masks needed from seven to six, improving efficiency and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masks are used to form gate, source, and drain layers separately, then the manufacturing precision and insulation are improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the formation of gate, source, and drain layers into a single mask process. The half-tone mask is designed with multiple pattern regions that simultaneously define all three layers, eliminating the need for separate masking steps for each layer and reducing overall process complexity
Solution Approach 2:
The half-tone mask employs different thickness regions (first thickness for gate, second thickness for source/drain) to achieve different etching depths and patterns in different areas. This local variation in mask properties enables precise control of each layer's geometry while using a single mask structure
2Manufacturing precision
If multiple masks are used for forming gate, source, and drain layers, then the manufacturing precision is improved, but the productivity decreases
Solution Approach 1:
Multiple layer formation operations are merged into one simultaneous mask process. The half-tone mask enables all three layers (gate, source, drain) to be defined in a single exposure and etching cycle, dramatically reducing the number of process steps and improving manufacturing throughput
Solution Approach 2:
The half-tone mask is pre-designed with specific thickness variations and pattern configurations that anticipate the different requirements of gate, source, and drain layers. This preliminary structuring of the mask allows all layers to be formed correctly in one step without requiring subsequent adjustment steps
3Manufacturing precision
If traditional mask processes are used, then the manufacturing precision is maintained, but the loss of time increases
Solution Approach 1:
The patent merges multiple sequential mask processes into a single parallel operation. By designing the half-tone mask to simultaneously define gate, source, and drain patterns, the total time required for layer formation is reduced from multiple sequential steps to one concurrent process step
4Productivity
If a simple mask process is used, then the productivity is improved, but the manufacturing precision deteriorates
Solution Approach 1:
The half-tone mask incorporates local quality variations with different thickness regions optimized for specific layers. The first thickness region provides precise gate definition while the second thickness region enables accurate source and drain formation, maintaining high precision for each layer within the simplified single-mask process
Solution Approach 2:
The mask utilizes parameter changes in thickness (first thickness vs. second thickness) to control the etching process differently for various layers. This parameter variation allows the single mask process to achieve the precision normally requiring multiple masks with different parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the self-aligned top gate structure, reduces parasitic capacitance, and prevents short circuits, while saving time and resources in the manufacturing process by simplifying the mask processes and ensuring better insulation and switching performance of TFTs.
Implementation Method 1
forming a gate insulating layer on the oxide film layer by using a half-tone mask
Implementation Method 2
etching on the second layer of metal by using a same mask process, to obtain a gate layer, and a source layer and a drain layer
Data Source
AI summary
The present application discloses a display panel preparation method and a display panel. The display panel preparation method includes: forming a first metal layer, a buffer layer, an oxide film layer, and a gate insulating layer on a substrate; and etching on a second layer of metal by using a same mask process, to obtain a gate layer, a source layer, and a drain layer.