IGZO Seed Layer Double-Structure Electrode for TFT Contact Resistance

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Solution Overview

Problem

Existing thin film transistors face challenges in improving electric characteristics due to high contact resistance between electrode layers and semiconductor layers, which affects the performance of display devices.

Innovation Solution

A thin film transistor with a double-layer electrode structure, where the seed layer is formed of indium gallium zinc oxide (IGZO) doped transparent conductive material and the main layer is made of transparent conductive materials like indium tin oxide (ITO), zinc oxide (ZnO), or tin oxide (SnO2), reducing contact resistance through a deposition and thermal annealing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single-layer electrode structure is used, then the device structure is simple, but the contact resistance between electrode layer and semiconductor layer is high

Engineering Contradiction:
Improvecontact resistanceVSAvoidelectrode structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The electrode layer is divided into two distinct layers: a seed layer made of IGZO-doped transparent conductive material in contact with the semiconductor layer, and a main layer made of transparent conductive material on top. This segmentation allows the seed layer to optimize contact resistance at the interface while the main layer provides overall conductivity, resolving the contradiction between simple structure and low contact resistance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The electrode structure uses composite materials by combining IGZO-doped transparent conductive material in the seed layer with transparent conductive material in the main layer. This composite approach leverages the specific properties of each material to achieve low contact resistance at the semiconductor interface while maintaining overall electrode functionality, thus improving reliability without excessive complexity.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution significantly reduces contact resistance and enhances the electric characteristics of the thin film transistor, improving resistivity, hall mobility, and carrier concentration, leading to better performance and stability of the device.

Implementation Method 1

The seed layer is formed of a transparent conductive material doped with indium gallium zinc oxide (IGZO)

Methodology Applied
Scientific EffectDoping: Dopants

Implementation Method 2

forming an electrode layer having a double layer structure on the gate insulation film

Methodology Applied
Scientific EffectDeposition: Deposition (physical)

Implementation Method 3

The forming of the electrode layer may be performed thickness a deposition process at normal temperature and a thermal annealing process at about 350° C.

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS8647932B2Manufacturing method of thin film transistor
Publication Date: 2014.02.11 SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
  • US8647932B2 patent drawing
  • US8647932B2 patent drawing
  • US8647932B2 patent drawing

AI summary

Disclosed are a thin film transistor and a method of manufacturing the thin film transistor. An electrode layer of the thin film transistor includes a seed layer formed of a transparent conductive material doped with indium gallium zinc oxide (IGZO) and a main layer formed of a transparent conductive material. The thin film transistor includes a substrate, a gate electrode on the substrate, a gate insulation film on the substrate to cover the gate electrode, a semiconductor layer disposed on the gate insulation film in a region corresponding to the gate electrode, an electrode layer having a double layer structure and disposed on the gate insulation film in a manner such that a topside portion of the semiconductor layer is exposed through the electrode layer, and a passivation layer on the gate insulation film to cover the semiconductor layer and the electrode layer.