IGZO Gate Transistor Structure for DRAM Leakage Suppression
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Solution Overview
Problem
In DRAM devices, neighboring gate structures' on-off operations can cause charges to not return to their original location, leading to data storage errors in capacitors connected to transistors, resulting in incorrect data recognition.
Innovation Solution
The use of a transistor structure with an active pattern defined by isolation patterns, a gate structure extending through these patterns, and oxide semiconductor patterns including In-rich IGZO and Ga-rich IGZO, which reduce leakage current and mitigate data recognition errors by preventing electron movement between source/drain regions during on-off operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If neighboring gate structures are operated in on-off mode, then switching function is achieved, but leakage current is generated and data recognition errors occur
Solution Approach 1:
An oxide semiconductor pattern is introduced as an intermediary layer between the gate structure and the active pattern. This intermediary layer suppresses the generation of leakage current by preventing charge induction into the active pattern during gate switching operations, thereby resolving the harmful effect while maintaining the switching function.
Solution Approach 2:
The electrical properties of the interface between the gate structure and active pattern are changed by introducing the oxide semiconductor pattern. This changes the charge distribution and electrical characteristics, preventing the leakage current generation mechanism that occurs in conventional structures during on-off operations.
2Device complexity
If gate structure extends through isolation patterns, then device integration is improved, but charge induction into active pattern occurs causing data errors
Solution Approach 1:
The oxide semiconductor pattern serves as a mediator between the extended gate structure and the active pattern. It allows the gate to extend through the isolation pattern for high integration while preventing the harmful charge induction into the active pattern, thus resolving the contradiction between integration and reliability.
3Ease of manufacture
If conventional transistor structure is used, then manufacturing is simpler, but leakage current cannot be suppressed
Solution Approach 1:
The invention uses a composite structure combining oxide semiconductor material with conventional semiconductor materials. This composite approach maintains manufacturing compatibility with existing processes while introducing the oxide semiconductor's unique properties to suppress leakage current, balancing ease of manufacture with harmful factor suppression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed transistor structure effectively reduces leakage current and prevents data recognition errors, ensuring accurate data storage and retrieval by maintaining charge stability during gate operations.
Implementation Method 1
charges induced into an active pattern by the on-off operation may not return to the original location
Data Source
AI summary
A transistor structure including an active pattern defined by a first isolation pattern on a substrate, a second isolation pattern at an upper portion of the active pattern, a gate structure extending through the active pattern and the first isolation pattern, at least a lower portion of the gate structure extending through the second isolation pattern, a first oxide semiconductor pattern on a lower surface and a sidewall of the gate structure, the first oxide semiconductor pattern including In-rich IGZO and at least partially contacting the first and second isolation patterns, and source/drain regions at upper portions of the active pattern adjacent to the gate structure may be provided.