IGZO Display Transistor Gate Electrode Oxygen Barrier
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Solution Overview
Problem
The manufacturing of display devices with thin film transistors faces challenges in achieving high charge-mobility while maintaining cost-effectiveness, as amorphous silicon has low charge-mobility and polycrystalline silicon requires complex and costly crystallization processes.
Innovation Solution
A display device is developed with an active pattern of indium-gallium-zinc oxide (IGZO) and a gate electrode structure featuring a triple-layer stack of gate barrier layers and metal layers, formed under specific oxygen partial pressure conditions to enhance transistor reliability and prevent oxidation, simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used for the active layer, then the manufacturing process is simple, but the charge-mobility is low
Solution Approach 1:
The patent employs a composite gate electrode structure consisting of multiple layers (gate barrier layer, gate electrode layer, and gate insulating layer) with different material compositions. This composite structure enables simultaneous achievement of simple manufacturing (using sputtering process) and high charge-mobility (through optimized material stack with IGZO active layer and appropriate barrier layers) without requiring complex crystallization processes
2Reliability
If polycrystalline silicon is used for the active layer, then the charge-mobility is high, but the manufacturing cost and process complexity increase
Solution Approach 1:
The patent changes the material parameters of the gate electrode structure by using a multi-layer composition with specific materials (gate barrier layer with same oxide as active pattern, gate electrode layer with metal, and gate insulating layer) and optimized thicknesses. This parameter optimization allows achieving high charge-mobility comparable to polycrystalline silicon while maintaining the manufacturing simplicity of amorphous silicon processes, avoiding complex crystallization steps
3Productivity
If a simple gate electrode structure is used, then the manufacturing process is efficient, but the transistor reliability and oxidation resistance are insufficient
Solution Approach 1:
The gate electrode is segmented into three distinct layers: gate barrier layer (preventing oxygen diffusion), gate electrode layer (providing electrical function), and gate insulating layer (providing electrical isolation). This segmentation allows each layer to perform its specific function optimally, achieving high oxidation resistance and transistor reliability while maintaining manufacturing efficiency through a single sputtering process sequence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the reliability and mobility of transistors by compensating for oxygen defects and preventing oxidation, resulting in a more efficient and cost-effective manufacturing process for display devices.
Implementation Method 1
forming an oxide semiconductor layer on a substrate under a low-oxygen partial pressure condition
Implementation Method 2
forming a first gate barrier layer including a same oxide as the active pattern on the active pattern under a high-O2 partial pressure condition
Data Source
AI summary
A display device includes a semiconductor member, a first gate electrode, a pixel electrode, and a common electrode. The semiconductor member includes a source area, a drain area, and a channel area between the source area and the drain area. The first gate electrode includes a first gate barrier layer, a second gate barrier layer, and a gate metal layer. The first gate barrier layer overlaps the channel area. An oxide material of the first gate barrier layer is identical to an oxide material of the semiconductor member. The second gate barrier layer includes a metal oxide alloy and is positioned between the first gate barrier layer and the gate metal layer. The pixel electrode is electrically connected to the drain area. The common electrode overlaps the pixel electrode.