IGZO GOA Circuit Negative Threshold Voltage Stabilization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The gate driver on array (GOA) circuit in IGZO thin film transistors is prone to failure due to a negative threshold voltage and sensitivity to positive bias temperature stress, leading to severe performance degradation and failure.
Innovation Solution
The GOA circuit incorporates a cascade structure with multiple units, including pull-up, pull-down, and bootstrap components, utilizing a network of TFTs and constant voltage sources to manage electrical potentials and prevent excessive negative threshold voltage, along with a bootstrap capacitor to stabilize signal levels and mitigate the effects of positive bias temperature stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional TFT circuit designs are used, then manufacturing process is simpler, but switching speed is insufficient for high refresh rate displays
Solution Approach 1:
The TFT circuit is divided into multiple sub-periods within the programming period, with different transistor groups activated in each sub-period. This segmentation allows incremental charging of the storage node, achieving faster effective switching speed while maintaining manageable circuit complexity through staged operation.
Solution Approach 2:
The circuit employs dynamic control of transistor activation states across multiple sub-periods, where transistor groups are selectively turned on and off to progressively charge the storage node. This dynamic operation enables the circuit to adapt its charging rate to achieve high-speed performance.
2Productivity
If programming period is shortened for high refresh rate, then display refresh capability improves, but charging time becomes insufficient
Solution Approach 1:
The programming period is segmented into multiple sub-periods, allowing the storage node to be charged in incremental stages. This segmentation enables sufficient total charging time to be achieved within a short overall programming period, supporting high refresh rates while ensuring complete charging.
Solution Approach 2:
Transistor groups are pre-configured and activated in specific sub-periods to prepare charge transfer paths in advance. This preliminary action ensures that charging can proceed efficiently through multiple stages without delay, maximizing the use of available programming time.
3Area of moving object
If transistor size is reduced for higher pixel density, then display resolution improves, but switching speed decreases
Solution Approach 1:
The charging operation is segmented across multiple sub-periods with different transistor groups, allowing small transistors to achieve sufficient charge transfer through cumulative action. This segmentation compensates for the reduced individual transistor capacity while maintaining high switching speed performance.
Solution Approach 2:
The charging process continues across multiple sub-periods without interruption, with each transistor group contributing to the cumulative charge. This continuous useful action ensures that even small transistors can achieve the required charge transfer for high-speed operation at high pixel densities.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An IGZO thin-film transistor GOA circuit, and display device. The GOA circuit comprises multiple cascaded GOA units, and an N-th stage GOA unit comprises a pull-up control unit (100), a pull-up unit (200), a pull-down unit (500), a pull-down holding unit (400), a transfer unit (300), a bootstrap capacitor (Cb), a first constant voltage source (VSS1) having a negative voltage level, and a second constant voltage source (VSS2) having a negative voltage level. The present invention addresses the problem of a high failure rate of GOA circuits composed of IGZO thin-film transistors.