IGZO Resistive Memory Element With Thermal Multi-State Programming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing programmable resistive memory elements with IGZO, such as those used in transparent thin film transistors, are limited by a small number of resistance states, which restricts their memory density and data capacity.
Innovation Solution
A programmable resistive memory element with a planar structure is developed, utilizing a local on-chip thermal treatment in air atmosphere to adjust resistance by applying voltage sweeps, increasing the number of resistance states through controlled heating and passivation of oxygen vacancies in the IGZO layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If voltage pulses are applied to set and reset oxygen vacancies in the IGZO layer, then resistance states can be adjusted, but the number of possible memory resistance states is limited
Solution Approach 1:
The patent applies parameter changes by utilizing voltage sweeps with varying high voltage limits (from few volts to few tens of volts) to create multiple resistance states. By changing the voltage parameter during sweeps, the patent achieves programmable resistance values without increasing structural complexity, directly resolving the contradiction between increasing resistance states and maintaining simple device structure.
2Quantity of substance
If local thermal treatment is applied to increase resistance states, then memory density and data capacity increase, but the process requires additional voltage sweeps and heating control
Solution Approach 1:
The patent employs self-service by using the memory element itself as the heating source through Joule heating during voltage sweeps. The local thermal treatment is achieved automatically by applying voltage sweeps to the resistive memory element, eliminating the need for external heating equipment and simplifying the programming operation while increasing memory density.
3Ease of manufacture
If conventional IGZO resistive memory elements are used, then integration with TFTs is easy and transparent memories can be realized, but the number of storage states is limited
Solution Approach 1:
The patent applies universality by maintaining the IGZO-based resistive memory element structure that is compatible with TFT integration and transparent memory applications, while simultaneously enabling multiple storage states through voltage sweep programming. This allows the same device structure to serve both the ease of manufacture requirement and the increased storage states requirement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the number of memory resistance states, enabling higher memory density and data capacity, with the memory element being nonvolatile and largely irreversible to reset to lower resistance states.
Implementation Method 1
The thermal treatment is obtained by locally heating of the resistive memory element and is performed by applying one or more voltage sweeps to the resistive memory element
Implementation Method 2
The set operation moves oxygen vacancies through the IGZO layer to form a conductive filament between top and bottom electrodes. The reset operation moves the oxygen vacancies so that the conductive filament is destroyed.
Data Source
AI summary
A programmable resistive memory element and a method of adjusting a resistance of a programmable resistive memory element are provided. The programmable resistive memory element includes at least one resistive memory element. Each resistive memory element includes an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer, a first electrical contact and a second electrical contact. The first and second electrical contacts are disposed on the IGZO resistive layer in the same plane. The programmable resistive memory element includes a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.