IGZO OSC Array Substrate CMOS Inverter Fabrication

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Solution Overview

Problem

The industry faces challenges in designing liquid crystal displays (LCDs) that incorporate both indium gallium zinc oxide (IGZO) and organic semiconductor (OSC) materials to enhance processing speed and reduce power consumption, while maintaining flexibility and low production costs.

Innovation Solution

A method of fabricating an array substrate that forms CMOS inverters or CMOS ring oscillators by alternately arranging IGZO and OSC patterns on a substrate, with specific metallic and insulating layers, and passivation layers to create N-channel and P-channel MOS transistors connected in series, enabling the integration of IGZO and OSC materials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If IGZO and OSC materials are integrated to fabricate CMOS inverters, then processing speed and power consumption are improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improveprocessing speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent segments the CMOS inverter into two distinct transistor types: first transistors using IGZO material (for high-speed N-channel functionality) and second transistors using OSC material (for P-channel functionality). This segmentation allows each material to be optimized for its specific role while maintaining overall CMOS functionality, resolving the contradiction by enabling speed improvement through IGZO without requiring complete device redesign.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by assigning different semiconductor materials to different spatial locations within the CMOS inverter structure. IGZO is used specifically in regions requiring high electron mobility (N-channel), while OSC is used in regions requiring hole transport (P-channel). This localized material assignment optimizes performance in each region while managing overall device complexity.

Inventive Principle:
Principle #3Local quality

2Use of energy by moving object

If IGZO and OSC materials are integrated to fabricate CMOS inverters, then power consumption is reduced, but manufacturing process complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoidease of manufacture
Core Design Contradiction:
Use of energy by moving objectVSEase of manufacture

Solution Approach 1:

The patent employs preliminary action by forming the IGZO patterns and OSC patterns in separate, sequential fabrication steps before final assembly. The IGZO transistor regions are prepared and processed first, followed by OSC transistor regions. This preliminary separation of material processing simplifies the manufacturing approach compared to attempting to process both materials simultaneously, making the integrated structure more manufacturable.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses an insulating layer as an intermediary between the IGZO and OSC components. This insulating layer facilitates the integration of the two different semiconductor materials by providing electrical isolation and structural separation, enabling manufacturers to work with each material system independently while achieving final integration, thus improving ease of manufacture.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of energy

If CMOS inverters are fabricated with IGZO and OSC materials, then quiescent power consumption is lowered, but fabrication process difficulty increases

Engineering Contradiction:
Improvequiescent power consumptionVSAvoidfabrication process difficulty
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent applies parameter changes by utilizing the distinct electrical and physical properties of IGZO and OSC materials in different transistor configurations. IGZO's high electron mobility is exploited in N-channel transistors for fast switching with low leakage, while OSC's characteristics are optimized for P-channel transistors. These parameter-based material selections enable low quiescent power consumption inherent to CMOS operation while managing fabrication complexity through material-property-matched design.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9899452B2Array substrate and method of fabricating the same
Publication Date: 2018.02.20 TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
  • US9899452B2 patent drawing
  • US9899452B2 patent drawing
  • US9899452B2 patent drawing

AI summary

The present invention proposes an array substrate and a method for fabricating the same. According to the array substrate and the method of fabricating the array substrate in the present invention, the IGZO pattern and the first electrode strip, the first channel, and the second metallic layer in the corresponding section form the first transistor of the CMOS inverter, and the OSC pattern and the second electrode strip, the second channel, and the second metallic layer in the corresponding section form the second transistor of the CMOS inverter. In this way, the CMOS inverter or the CMOS ring oscillator is fabricated based on IGZO and OSC.