IGZO TFT Substrate with Al2O3 Buffer Layer for Defect Reduction

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Solution Overview

Problem

The existing manufacturing processes for top gate type IGZO thin film transistors suffer from defects in the contact surface between the active layer and the gate insulating layer due to exposure to photoresist and organic solvents, leading to instability in OLED and Micro LED devices.

Innovation Solution

A first insulating layer is deposited before patterning the metal oxide semiconductor layer, serving as a protective layer to reduce defects and improve stability, and is patterned using a dry etching method, while the second insulating layer and gate metal layer are patterned using a top gate self-aligned technology to form a gate insulating layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a top gate type IGZO TFT fabrication process is used, then high mobility and current driving capability are achieved, but the contact surface between the active layer and gate insulating layer develops defects due to exposure to photoresist and organic solvents

Engineering Contradiction:

Improvedevice stabilityVSAvoidcontact surface defects

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An aluminum oxide (Al2O3) insulating layer is introduced as an intermediary protective layer between the IGZO active layer and the gate insulating layer. This intermediary layer prevents direct contact between the active layer and harmful substances (photoresist, organic solvents) used during fabrication, thereby eliminating contact surface defects while maintaining the top gate structure's high mobility advantages

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The aluminum oxide layer creates an inert protective environment for the IGZO active layer during subsequent fabrication processes. This inert barrier prevents chemical interactions and contamination from photoresist and organic solvents, ensuring the active layer remains free from defects that would compromise device stability

Inventive Principle:

Principle #39Inert atmosphere (Inert environment)

2Device complexity

If a conventional bottom gate structure is used, then the fabrication process is simpler, but a large parasitic capacitance is generated due to large overlapping area between gate and source/drain electrodes

Engineering Contradiction:

Improvefabrication process complexityVSAvoidsignal delay

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent inverts the conventional bottom gate structure to a top gate structure, where the gate electrode is positioned above the active layer rather than below. This inversion eliminates the overlapping area between gate and source/drain electrodes, thereby removing the source of parasitic capacitance and signal delay while maintaining fabrication feasibility

Inventive Principle:

Principle #13The other way round (Inversion)

3Reliability

If a top gate self-aligned structure is used, then parasitic capacitance is reduced and ductility is improved, but the active layer is exposed to more photoresist and organic solvents during fabrication

Engineering Contradiction:

Improvedevice ductilityVSAvoidexposure to photoresist and organic solvents

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The aluminum oxide insulating layer is deposited preliminarily on the IGZO active layer before the top gate self-aligned fabrication process begins. This preliminary protective action ensures that when photoresist and organic solvents are subsequently applied during patterning, the active layer is already shielded, preventing contamination while allowing the self-aligned structure's ductility benefits to be realized

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the stability of the thin film transistor substrate by reducing defects on the contact surface, improving device performance under positive and negative bias temperature stress tests.

Implementation Method 1

step S1, providing a substrate, and sequentially depositing a buffer layer, a metal oxide semiconductor layer, and a first insulating layer on the substrate

Methodology Applied

Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Implementation Method 2

The first insulating layer and the metal oxide semiconductor layer are patterned according to a pattern of an active layer

Methodology Applied

Scientific EffectDry etching:

Data Source

PatentUS11374027B2Manufacturing method of thin film transistor substrate and thin film transistor substrate

Publication Date: 2022.06.28 SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD

AI summary

A manufacturing method of a thin film transistor substrate and a thin film transistor substrate are provided. In the manufacturing method of the thin film transistor substrate, a buffer layer, a metal oxide semiconductor layer, and a first insulating layer are sequentially deposited on a substrate, and then the first insulating layer and the metal oxide semiconductor layer are patterned according to a pattern of an active layer. The metal oxide semiconductor layer forms the active layer. A second insulating layer and a gate metal layer are then sequentially deposited. The first insulating layer and the second insulating layer together form a gate insulating layer. The first insulating layer can be used to protect the metal oxide semiconductor layer, such that defects on a contact surface between the active layer and the gate insulating layer are reduced, thereby improving the stability of a device.