IGZO TFT Array Substrate Manufacturing via Halftone Photomask Etching

The patent divides the etching process into multiple stages: a first etching process to form the channel structure, and a second etching process to remove photoresist. By segmenting the etching operations and applying different etchants at different stages, the process achieves precise channel formation while preventing over-etching of the IGZO layer and source/drain electrodes.

The patent applies a protective layer (such as silicon oxide or silicon nitride) to the IGZO layer before the etching process. This preliminary protective action prevents the IGZO from being over-etched during the channel formation process, while still allowing the etchant to access and etch the source and drain electrode metal layer through the protective layer.

The patent combines multiple etching operations into a unified process flow where the first etching process simultaneously defines the channel structure and prepares the surface for the second etching process. The protective layer serves multiple functions: protecting IGZO during etching, defining the channel boundary, and enabling selective removal of photoresist in the second etching process.

The protective layer acts as an intermediary element that mediates between the etchant and the IGZO layer. It allows the etchant to selectively access the source and drain electrode metal layer while blocking the IGZO layer, thereby enabling precise channel definition without requiring complex masking and multiple separate etching processes.