IGZO TFT Light-Shielding Layout for Lower Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing OLED array substrates based on IGZO TFTs face issues of high resistance and reduced on-state current due to insufficient conductive treatment of the active layer, particularly when the light-shielding layer is thick or steep, leading to increased power consumption and lower screen brightness.
Innovation Solution
The implementation of a thin film transistor design that includes a light-shielding layer with specific patterns extending to the conductive areas, ensuring comprehensive coverage and reducing parasitic capacitance, thereby facilitating effective conductive treatment and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the light-shielding layer is made thick (above 6500 Å) or with steep taper (above 60°) to improve light-shielding performance, then light-shielding effectiveness is improved, but IGZO conductive treatment becomes insufficient leading to high resistance
Solution Approach 1:
The light-shielding layer is divided into multiple segments with different thicknesses and taper angles. The first light-shielding pattern has a first thickness and first taper angle, while the second light-shielding pattern has a second thickness and second taper angle, allowing different regions to serve different functions - some regions provide strong light-shielding while others facilitate proper IGZO conductive treatment
Solution Approach 2:
Different regions of the light-shielding layer are given different local properties. By varying the thickness and taper angle in different areas, the structure optimizes light-shielding performance where needed while maintaining areas that allow proper IGZO conductive treatment, thus resolving the contradiction between light-shielding effectiveness and conductive treatment completeness
2Area of stationary object
If the light-shielding layer boundary is placed close to the gate boundary (within 4 μm) to reduce device area, then device area is reduced, but photoresist blocking occurs making etching and conductive treatment difficult
Solution Approach 1:
The light-shielding layer is segmented into multiple patterns with different geometries and positions. This segmentation allows the boundary regions to be designed with specific characteristics that prevent photoresist blocking while maintaining compact device area, enabling proper access for etching and conductive treatment
3Device complexity
If conventional single-pattern light-shielding layer is used to simplify structure, then structure complexity is reduced, but IGZO climbing the slope causes insufficient conductive treatment
Solution Approach 1:
The light-shielding layer is divided into multiple segments (first light-shielding pattern and second light-shielding pattern) with different thicknesses and taper angles. This segmentation prevents IGZO from climbing the slope by creating controlled interfaces, ensuring proper conductive treatment while maintaining reasonable structural complexity
Solution Approach 2:
The buffer layer serves as an intermediary between the light-shielding layer and the IGZO active layer. It provides a transition zone that prevents IGZO from climbing the light-shielding layer slope, ensuring proper conductive treatment of the IGZO while maintaining the necessary light-shielding functionality
Data Source
AI summary
A thin film transistor and an array substrate, including a light-shielding layer and an active layer. The light-shielding layer includes a first light-shielding pattern, a second light-shielding pattern and a third light-shielding pattern. The active layer includes a channel area, a first conductive area and a second conductive area located on both sides of the channel area. An orthogonal projection of the first light-shielding pattern on the substrate at least covers an orthogonal projection of the channel area on the substrate. An orthographic projection of the second light-shielding pattern on the substrate overlaps at least a part of an orthographic projection of the first conductive area on the substrate. An orthographic projection of the third light-shielding pattern on the substrate overlaps at least a part of an orthographic projection of the second conductive area on the substrate.