IGZO TFT Memory Cell Selector for Higher BEOL Density
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Solution Overview
Problem
The size limitation of CMOS transistors is a bottleneck in improving the size and memory cell density of memory devices, limiting the integration of memory cell elements such as MRAM and RRAM.
Innovation Solution
Employing surrounding gate thin film transistors (TFTs), specifically Indium-Gallium-Zinc-Oxide (IGZO) TFTs, as selecting transistors to form memory cell selectors, allowing for higher memory cell density by integrating them in the back-end-of-line (BEOL) fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMOS transistors are used as select transistors in memory cells, then the memory device can be fabricated using conventional processes, but the device density is limited due to the minimum size of CMOS transistors
Solution Approach 1:
The patent changes the material parameter of the transistor from conventional CMOS semiconductor to oxide semiconductor (IGZO), which enables smaller transistor dimensions while maintaining electrical performance. This material parameter change allows the select transistor to occupy less area, thereby increasing device density without sacrificing fabrication compatibility through low-temperature processing
Solution Approach 2:
The patent transitions from planar transistor architecture to vertically stacked three-dimensional structure, where the oxide semiconductor channel is arranged in a vertical configuration. This dimensional change enables higher integration density by utilizing the vertical space above the substrate, allowing multiple memory cells to be stacked and increasing the quantity of memory elements per unit area
2Quantity of substance
If individual transistors are made smaller to increase areal density, then the areal density improves, but the rate of further miniaturization is slowing
Solution Approach 1:
The patent fundamentally changes the semiconductor material parameter from silicon-based CMOS to oxide semiconductor (IGZO), which has different physical properties enabling smaller feature sizes. This material parameter transition allows continued miniaturization beyond the limits of conventional CMOS, maintaining a high productivity of miniaturization by leveraging the inherent scalability of thin-film oxide semiconductor processes
Solution Approach 2:
The patent replaces the conventional CMOS transistor mechanism with a thin-film oxide semiconductor transistor mechanism that can be fabricated using low-temperature deposition processes. This substitution enables smaller transistor dimensions and higher areal density while maintaining manufacturing productivity through established thin-film fabrication techniques rather than requiring advanced lithographic miniaturization
Data Source
AI summary
A memory structure, device, and method of making the same, the memory structure including: a channel comprising a semiconductor material; a source electrode electrically connected to a first end of the channel; a drain electrode electrically connected to an opposing second end of the channel; a high-k dielectric layer surrounding the channel; a gate electrode surrounding the high-k dielectric layer; and a memory cell electrically connected to the drain electrode and a bit line. The memory cell includes a first electrode that is electrically connected to the drain electrode.