IGZO Thin-Film Transistor Stack for Mobility and Reliability

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Solution Overview

Problem

Current thin film transistors and display devices face challenges in achieving improved element characteristics, particularly in terms of electron mobility and reliability, due to limitations in the design and manufacturing methods of semiconductor layers and insulating layers.

Innovation Solution

A thin film transistor design incorporating a semiconductor layer with indium gallium zinc oxide, a dummy layer of indium oxide, and specific insulating layers, along with a manufacturing method that includes surface treatment and precise layer formation to enhance channel area characteristics and electron mobility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional thin film transistor structures are used, then manufacturing is simpler, but electron mobility and reliability are insufficient

Engineering Contradiction:
Improveelement characteristicVSAvoidtransistor structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The transistor is divided into distinct functional regions: a semiconductor layer with differentiated first and second areas, a gate electrode, source/drain electrodes, and multiple insulating layers (first, second, and third insulating layers). This segmentation allows each region to be optimized independently for its specific function, improving overall device performance and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The semiconductor layer exhibits local quality variations with different properties in the first area versus the second area, enabling different functional characteristics in different regions. The dummy layer is strategically positioned to provide localized electrical connection optimization. This local differentiation enhances electron mobility and device reliability without requiring complete structural redesign.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If conventional manufacturing methods are used, then production is faster, but manufacturing precision of semiconductor layers is insufficient

Engineering Contradiction:
Improvesemiconductor layer formationVSAvoidmanufacturing speed
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

A dummy layer is formed in advance before the semiconductor layer deposition. This preliminary structure serves as a foundation that guides subsequent manufacturing steps, ensuring precise alignment and positioning of the semiconductor layer. The dummy layer is later removed after serving its guiding function, allowing high precision without permanent structural complexity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy layer acts as an intermediary element during manufacturing. It provides a temporary reference structure that facilitates precise semiconductor layer formation through techniques such as shadow masking or alignment guidance. Once the semiconductor layer is successfully formed with high precision, the dummy layer is removed, having fulfilled its mediating role without becoming part of the final device.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240234580A9Thin film transistor, manufacturing method of the same, and display device having the same
Publication Date: 2024.07.11 SAMSUNG DISPLAY CO LTD
  • US20240234580A9 patent drawing
  • US20240234580A9 patent drawing
  • US20240234580A9 patent drawing

AI summary

A transistor may include a first insulating layer disposed on a substrate, a dummy layer disposed on the first insulating layer, a semiconductor layer disposed on the dummy layer, the semiconductor layer including a first area, a second area, and a channel area disposed between the first and second areas, a second insulating layer disposed on the semiconductor layer, a gate electrode overlapping the channel area with the second insulating interposed therebetween, a third insulating layer disposed over the gate electrode, a first electrode disposed on the third insulating layer, the first electrode being electrically connected to the first area, and a second electrode disposed on the third insulating layer spaced apart from the first electrode, the second electrode being electrically connected to the second area. The dummy layer may include indium oxide, and the semiconductor layer may include indium gallium zinc oxide.