IGZO Thin Film Transistor Preparation via Simultaneous Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for preparing IGZO thin film transistors are complex and time-consuming, which hinders the development of high-quality, low-cost large-size and high-resolution liquid crystal display panels.
Innovation Solution
A method involving multiple mask steps to form a grid electrode, insulating layer, IGZO semiconducting layer, and metal layers, with hydrogen peroxide etching to simultaneously process the metal and IGZO layers, reducing the number of processing steps and enhancing manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional separate etching processes are used for metal layer and IGZO layer, then etching precision can be controlled, but manufacturing time increases and process complexity increases
Solution Approach 1:
The patent combines the etching of the metal layer and IGZO layer into a single simultaneous wet etching process using hydrogen peroxide solution. This merging of previously separate etching steps reduces manufacturing time and process complexity while maintaining acceptable etching precision through controlled solution concentration and temperature parameters.
Solution Approach 2:
The hydrogen peroxide solution serves as a universal etchant that can simultaneously etch both the metal layer and IGZO layer with different etching rates. This multi-functional etchant replaces the need for multiple specialized etching solutions and processes, streamlining the manufacturing workflow.
2Manufacturing precision
If multiple separate processing steps are used for metal layer and IGZO layer, then layer control is improved, but process complexity increases and productivity decreases
Solution Approach 1:
The patent merges multiple separate processing steps (metal layer etching and IGZO layer etching) into a single simultaneous wet etching process. This consolidation maintains layer control through selective etching rates while significantly improving manufacturing efficiency by reducing the total number of processing steps.
Solution Approach 2:
The patent utilizes parameter changes in the etching process, specifically controlling the concentration of hydrogen peroxide solution and temperature, to achieve different etching rates for the metal layer and IGZO layer. This allows simultaneous processing while maintaining precise layer control through parameter optimization.
3Speed
If IGZO material is used instead of AS material, then mobility and charging speed are improved, but manufacturing complexity increases
Solution Approach 1:
The patent changes the material parameter from traditional AS to IGZO semiconductor layer, which provides superior mobility and charging speed. To manage the associated manufacturing complexity, the patent employs simplified wet etching processes and optimizes deposition parameters to make IGZO processing more compatible with existing manufacturing workflows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the manufacturing process, reduces preparation time, and improves product yield by allowing simultaneous etching of metal and IGZO layers, thereby facilitating the production of high-resolution displays with reduced backlight consumption.
Implementation Method 1
simultaneously etching the second metal layer (4) and the IGZO semiconducting layer (3) by hydrogen peroxide
Implementation Method 2
The photoresist of the first channel region is specifically removed by ashing which performed with oxygen plasma
Implementation Method 3
the IGZO semiconducting layer is forming by physical vapor deposition
Data Source
AI summary
A method of preparing IGZO thin film transistor is provided. The method includes. step S1, using a first mask on a first metal layer to form a grid electrode, and sequentially forming grid insulating layer, IGZO semiconducting layer and second metal layer on grid electrode; step S2, coating photoresist layer on second metal layer, and exposure developing photoresist layer by second mask, and simultaneously etching second metal layer and IGZO semiconducting layer by hydrogen peroxide, and second metal layer is formed to source electrode and drain electrode by etching; step S3, forming passivation layer on source electrode and drain electrode, and forming a via hole above drain electrode by third mask; step S4, forming pixel electrode on passivation layer by fourth mask, and pixel electrode is connecting to drain electrode by via hole.