III-N 2-DEG Resistor Layout for Uniform Multi-Rs HEMT ICs
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Solution Overview
Problem
The uniformity of 2-DEG resistor resistance in III-N ICs is affected by the epitaxial growth, doping composition, and etching process of the topside group III-V layer, leading to degradation in resistance uniformity across the IC.
Innovation Solution
The implementation of a lower group III-N layer with a first composition over a substrate and an upper group III-N layer with a different second composition, where a gate electrode of a HEMT is located over the upper layer, and unbiased group III-N cover layers are used in resistor areas to achieve high and low Rs 2-DEG resistors without the need for additional mask levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a blanket etch is used to remove the topside group III-V layer above the 2-DEG resistors, then the 2-DEG resistors can be formed, but the uniformity of the 2-DEG resistor resistance is degraded due to overetch conditions
Solution Approach 1:
The patent segments the resistor formation process by creating distinct etch regions: a first etch region where the topside group III-V layer is completely removed to form low Rs resistors, and a second etch region where the layer is partially retained to form high Rs resistors. This segmentation allows different resistor types to be formed in the same etch cycle without compromising uniformity, as each region experiences the appropriate amount of etching for its intended function.
2Adaptability or versatility
If the topside group III-V layer is etched to form 2-DEG resistors, then resistors can be integrated on the IC, but the etching process causes non-uniform resistance across the IC die
Solution Approach 1:
The patent applies local quality by assigning different etching depths to different spatial regions on the IC die. The first etch region receives complete removal of the topside group III-V layer while the second etch region retains part of the layer. This localized differentiation enables both high Rs and low Rs resistors to coexist on the same die with各自 optimized resistance values, improving overall device reliability while maintaining integration versatility.
3Adaptability or versatility
If additional mask levels are used to fabricate resistors with different nominal Rs values, then different Rs values can be achieved, but the device complexity and manufacturing process are increased
Solution Approach 1:
The patent makes the single etch process universal by enabling it to perform multiple functions: forming both high Rs and low Rs resistors, as well as defining HEMT active regions, all in one etching cycle. The selective retention or removal of the topside group III-V layer in different regions allows this multi-functionality without requiring additional mask levels, thereby reducing device complexity while maintaining the versatility to fabricate different resistor types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the resistance uniformity of 2-DEG resistors across the IC, allows for the fabrication of resistors with different nominal Rs values on the same IC die, and reduces the area required for high Rs resistors, thereby enhancing device performance and efficiency.
Implementation Method 1
the piezopolarization charge present at the AlGaN/GaN heterostructure results in a high electron density in the 2-DEG layer
Implementation Method 2
a blanket etch may be used to remove all the topside III-V layer above the 2-DEG resistors to expose the barrier layer
Data Source
AI summary
An integrated circuit (IC) includes a lower group III-N layer having a first composition over a substrate, and an upper group III-N layer having a different second composition over the lower group III-N layer. A gate electrode of a High Electron Mobility Transistor (HEMT) is located over the upper group III-N layer. First and second resistor contacts make a conductive connection to the lower group III-N layer. An unbiased group III-N cover layer is located on the upper group III-N layer in a resistor area including a high Rs 2-DEG resistor, where the unbiased group III-N cover layer is positioned between the first and second contacts.