III-N Semiconductor Deposition on Lamellar Chalcogenide Layers
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Solution Overview
Problem
Current methods for manufacturing electronic devices based on semiconductor materials, such as III-N materials, are expensive and complex due to issues like buffer layer rupture during cooling steps, which complicates lattice parameter matching and increases costs.
Innovation Solution
A method involving the formation of a lamellar dichalcogenide or chalcogenide layer on a substrate, followed by physical vapor deposition of a III-N material and a thermo-chemical treatment to convert van der Waals bonds into covalent bonds, reducing substrate delamination and improving lattice matching without the need for expensive single-crystal silicon substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If buffer layers are used to achieve lattice parameter matching between silicon substrate and III-N semiconductor layers, then lattice matching is improved, but the buffer layers are subject to rupture problems during cooling steps
Solution Approach 1:
The patent introduces a lamellar chalcogenide layer as an intermediary between the silicon substrate and the III-N semiconductor layer. This intermediary layer with its unique lamellar structure and tunable lattice parameters serves as a buffer that accommodates lattice mismatch without the rupture problems associated with traditional buffer layers, thus resolving the contradiction between achieving lattice matching and maintaining buffer layer integrity
Solution Approach 2:
The patent utilizes the ability to tune the lattice parameters of the lamellar chalcogenide layer by selecting different chalcogenide materials and controlling deposition conditions. This parameter adjustment allows optimal lattice matching with both the silicon substrate and the III-N layer, achieving high manufacturing precision while avoiding buffer layer rupture during thermal cycling
2Manufacturing precision
If current manufacturing methods with buffer layers are used, then lattice matching can be achieved, but the manufacturing process becomes expensive and complex
Solution Approach 1:
The lamellar chalcogenide layer serves as a simplified intermediary that replaces complex multi-layer buffer structures. Its unique properties allow it to perform multiple functions (lattice matching, stress management, thermal expansion compensation) in a single layer, thereby reducing manufacturing process complexity while maintaining high lattice matching precision
Solution Approach 2:
The patent employs composite material structures where the lamellar chalcogenide layer combines different materials with complementary properties. This composite approach enables simultaneous achievement of lattice matching, mechanical stability, and thermal compatibility, simplifying the overall manufacturing process while maintaining high precision
3Shape
If van der Waals bonds between sheets in the lamellar layer are present, then the layer structure is formed, but the mechanical resistance and adhesion are reduced
Solution Approach 1:
The patent applies thermal treatment to change the bonding parameters within the lamellar chalcogenide layer. By controlling temperature and atmosphere during annealing, the van der Waals bonds between sheets are transformed into stronger covalent bonds, thereby enhancing mechanical resistance and adhesion while preserving the essential lamellar structure
Solution Approach 2:
The patent implements localized thermal treatment that selectively strengthens specific regions of the lamellar layer. The annealing process is controlled to convert van der Waals bonds to covalent bonds in critical areas where mechanical strength is needed, while maintaining the lamellar structure in other regions, thus achieving local optimization of both structure and strength
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases the cost of electronic devices by eliminating the need for single-crystal silicon substrates and enhances mechanical resistance by improving adhesion and crystal texturing, while avoiding buffer layer delamination.
Implementation Method 1
forming, by physical vapor deposition on the side of said surface of the support substrate, a second layer made of a first III-N material coating the first layer
Implementation Method 2
at step c), the thermo-chemical treatment is an anneal carried out under a reducing atmosphere
Implementation Method 3
carrying out a thermo-chemical treatment of the first layer resulting, in the first layer, in a conversion of van der Waals bonds between the sheets of the first layer into covalent bonds
Data Source
AI summary
A method including the following successive steps: a) forming, on a surface of a support substrate, a first layer made of a material selected from among a lamellar dichalcogenide or a lamellar chalcogenide including a stack of sheets; b) forming, by physical vapor deposition on the side of said surface of the support substrate, a second layer made of a first III-N semiconductor material coating the first layer; and c) carrying out a thermo-chemical treatment of the first layer resulting, in the first layer, in a conversion of van der Waals bonds between the sheets of the first layer into covalent bonds.