III-N Transistor Contact Layout for Lower Off-State Capacitance
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Solution Overview
Problem
III-N transistors face challenges in large-scale implementation due to non-negligible off-state capacitance, which hinders their performance in high-frequency switch applications, particularly in millimeter-wave wireless technologies like 5G.
Innovation Solution
The design of III-N transistors with source/drain contacts and gate contacts of reduced width, which minimizes the overlap area between these contacts, thereby reducing off-state capacitance and enhancing switching frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contacts are made with standard width to ensure adequate electrical connection, then electrical conductivity is maintained, but off-state capacitance increases which reduces switching frequency performance
Solution Approach 1:
The patent applies local quality by making the contact width variable along its length. The contact has a narrower width in the region overlapping with the gate electrode and a wider width in regions away from the gate. This localized modification reduces off-state capacitance in the critical overlap region while maintaining adequate electrical connection in the non-overlapping regions, thus resolving the contradiction between connection quality and switching frequency.
2Productivity
If contact width is reduced to minimize overlap area and reduce off-state capacitance, then switching frequency increases, but electrical connection quality may deteriorate
Solution Approach 1:
The contact structure uses local quality by implementing different widths at different positions. The narrowed width is applied specifically in the region where the contact overlaps with the gate electrode, which is the region contributing to off-state capacitance. The wider width is maintained in regions that do not overlap with the gate, ensuring adequate electrical connection. This localized differentiation allows the contact to simultaneously achieve low capacitance and good connection quality.
Data Source
AI summary
Disclosed herein are IC structures, packages, and devices that include transistors, e.g., III-N transistors, having a source region, a drain region (together referred to as “source/drain” (S/D) regions), and a gate stack. In one aspect, a contact to at least one of the S/D regions of a transistor may have a width that is smaller than a width of the S/D region. In another aspect, a contact to a gate electrode material of the gate stack of a transistor may have a width that is smaller than a width of the gate electrode material. Reducing the width of contacts to S/D regions or gate electrode materials of a transistor may reduce the overlap area between various pairs of these contacts, which may, in turn, allow reducing the off-state capacitance of the transistor. Reducing the off-state capacitance of III-N transistors may advantageously allow increasing their switching frequency.