III-N Semiconductor Surface Defect Planarization via Dielectric Filling
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Solution Overview
Problem
High-power devices made from III-N semiconductor materials, such as GaN, face premature breakdown due to surface defects like 'inverted pyramid' type defects, which increase electric fields and reduce performance, and existing solutions like increasing thickness or using CMP processes are costly and fragile, or reduce crystalline quality.
Innovation Solution
A process involving the deposition of a barrier layer of a second III-N material with a greater bandgap, followed by dielectric layers to fill surface defects, and a CMP etching operation to create a flat surface, allowing for the production of devices with reduced defect impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the total thickness of the structure is significantly increased to reduce the effect of surface defects, then the breakdown voltage performance is improved, but the fragility of the component and manufacturing cost increase
Solution Approach 1:
The patent divides the structure into multiple functional layers: a first III-N material layer containing surface defects, a barrier layer of second III-N material, and a dielectric layer. This segmentation isolates the defective region from the active device area, preventing defect propagation while maintaining overall device reliability without increasing total thickness.
Solution Approach 2:
The barrier layer of second III-N material acts as an intermediary between the defective first III-N material layer and the dielectric layer. This intermediate layer prevents direct interaction between the defect and the dielectric, eliminating the harmful electric field concentration while allowing the dielectric to perform its insulating function.
2Reliability
If a thick layer of III-N material is deposited followed by CMP etching to eliminate surface defects, then the breakdown voltage performance is improved, but the component fragility and manufacturing cost increase
Solution Approach 1:
The patent extracts the defective surface region by depositing the barrier layer conformally over the defects. The subsequent CMP process selectively removes the barrier layer and dielectric material from defect-free areas, leaving the defect-containing region isolated. This extraction approach eliminates defects without requiring thick material deposition or complex multi-step CMP processes.
3Manufacturing precision
If the crystalline quality of GaN is reduced by lowering deposition temperature to decrease surface defects, then the density of inverted pyramid defects is reduced, but the substrate curvature increases beyond tolerance
Solution Approach 1:
The patent performs preliminary conformal deposition of the barrier layer of second III-N material over the defective surface before any planarization or defect removal steps. This preliminary action preserves the original substrate curvature and defect distribution, allowing subsequent selective CMP to remove defects without inducing additional warpage from low-temperature deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively fills surface defects, preventing premature breakdown and maintaining device integrity and performance, especially under high voltages, without increasing fragility or manufacturing costs.
Implementation Method 1
said second III-N material having a gap between the valence band and the conduction band greater than the gap between the valence band and the conduction band of said first III-N material
Implementation Method 2
the deposits of at least two layers of different dielectric materials on the surface of said barrier layer of semiconductor material made of III-N material and filling said surface defects of crystallographic growth
Implementation Method 3
a 'CMP' etching operation defining a set of materials
Data Source
AI summary
The invention relates to a method for producing a device comprising at least one layer made of III-N semiconductor material having crystal-growth surface defects and a substrate, the method comprising: - depositing a barrier layer made of a second III-N material on the surface of a layer of a first III-N semiconductor material, said second III-N material having a larger gap between the valence band and the conduction band than the gap between the valence band and the conduction band of the first III-N material; - depositing at least two layers of different dielectric materials on the surface of said semiconductor material layer made of III-N material and filling said crystal-growth surface defects; - a "CMP" etching operation defining an assembly of materials; and - producing at least one contact at the surface of said assembly of materials. The device can be a transistor. The method can advantageously comprise a plurality of depositions of dielectric materials which can be SiN and SiO2.