III-N Devices in Si Trenches for Co-Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The co-integration of III-N material based devices with silicon (Si) substrates is challenging due to lattice mismatch and thermal expansion coefficient differences, leading to high defect densities and surface cracks, which hinder the integration of III-N transistors with Si CMOS circuits and complicate high-volume production.
Innovation Solution
The method involves forming trenches on a Si substrate, depositing a nucleation layer, and growing III-N material laterally over these trenches to create islands, which reduces defect density and eliminates the need for thick buffer layers, allowing for the co-integration of III-N devices with Si CMOS circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If III-N material is grown on Si substrate using conventional blanket epitaxial growth, then the entire Si wafer can be processed, but high defect densities and surface cracks occur due to lattice mismatch and thermal expansion differences
Solution Approach 1:
The patent divides the Si substrate into discrete trenches separated by Si CMOS circuit regions. III-N material is grown only within these trenches rather than across the entire wafer, segmenting the growth area to avoid defects while maintaining manufacturability. This selective area growth within trenches resolves the contradiction by limiting defect propagation to isolated regions.
Solution Approach 2:
The patent applies different material growth strategies to different regions: Si CMOS circuits are fabricated on the bulk Si substrate while III-N material is grown only in specific trench regions. This local differentiation allows each region to be optimized for its specific function, achieving high reliability in III-N devices without compromising the overall manufacturing process.
2Reliability
If thick and complex buffer layers are used to grow III-N material on Si, then material quality improves, but manufacturing time increases significantly
Solution Approach 1:
The trench structure segments the growth region, allowing III-N material to be grown directly on Si within the trench confines without requiring thick buffer layers. The trench walls provide physical containment that enables high-quality material growth in a time-efficient manner, eliminating the need for prolonged buffer layer deposition.
Solution Approach 2:
The trenches are formed in the Si substrate before III-N material growth begins. This preliminary structuring creates predefined growth zones that guide material deposition, ensuring high material quality from the start without requiring subsequent thick buffer layer formation to correct substrate mismatches.
3Adaptability or versatility
If blanket epitaxial growth is used over the entire Si wafer, then complete coverage is achieved, but co-integration of Si CMOS circuits and III-N devices side by side is not possible
Solution Approach 1:
The patent segments the Si wafer surface into distinct regions: trenches for III-N device growth and surrounding areas for Si CMOS circuit fabrication. This spatial segmentation enables both III-N devices and Si CMOS circuits to coexist on the same wafer, achieving co-integration while maintaining appropriate growth area for each device type.
Solution Approach 2:
Different regions of the wafer are assigned different functions: trench regions are optimized for III-N material growth while non-trench regions are optimized for Si CMOS processing. This local specialization enables versatile co-integration of different device types on a single wafer without compromising the area available for each technology.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach mitigates defect density and surface cracks, enabling the co-integration of III-N devices with Si CMOS circuits while reducing manufacturing time and costs, suitable for high-volume production of SoC products.
Implementation Method 1
depositing a nucleation layer on the first portion of the substrate within the trench
Implementation Method 2
the III-N material layer is laterally grown over the trench
Data Source
AI summary
A trench comprising a portion of a substrate is formed. A nucleation layer is deposited on the portion of the substrate within the trench. A III-N material layer is deposited on the nucleation layer. The III-N material layer is laterally grown over the trench. A device layer is deposited on the laterally grown III-N material layer. A low defect density region is obtained on the laterally grown material and is used for electronic device fabrication of III-N materials on Si substrates.