III-N and Silicon Cascode Integration on Leadframe
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Solution Overview
Problem
The increasing number of packages in cascoded semiconductor components leads to higher costs and degraded performance due to parasitic capacitance and inductance, necessitating a cost-efficient method for manufacturing these devices.
Innovation Solution
A semiconductor component and method involving a III-N based semiconductor chip coupled with a silicon based chip, using a leadframe with integrated device receiving areas and leadframe leads, and insulated metal substrates bonded with conductive materials to reduce packaging complexity and parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate packages are used to protect silicon and III-N devices, then device protection is achieved, but manufacturing cost increases and performance degrades due to parasitic effects
Solution Approach 1:
The patent combines multiple separate device packages into a single integrated package structure. The leadframe contains both the silicon device and III-N depletion mode device within one package, eliminating the need for separate packages and interconnecting them externally. This merging approach reduces packaging complexity while maintaining device protection through the unified package structure.
2Reliability
If multiple separate packages are used to protect silicon and III-N devices, then device protection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent integrates multiple devices into a single package, reducing the total number of packages required. This consolidation decreases manufacturing complexity and associated costs, including fewer packaging materials, reduced assembly steps, and simplified testing procedures, while still providing adequate protection for both silicon and III-N devices within the unified package.
3Ease of operation
If multiple separate packages are used to connect devices via leadframe leads, then device interconnection is achieved, but parasitic capacitance and inductance increase
Solution Approach 1:
The patent places both devices within a single package, significantly shortening the interconnection paths between devices. This integration reduces the length of leadframe leads required for interconnection, thereby minimizing parasitic capacitance and inductance. The devices remain properly interconnected through the leadframe structure while experiencing reduced harmful parasitic effects due to the compact integrated design.
Data Source
AI summary
In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads and at least one insulated metal substrate bonded to a first portion of the device receiving area. A first semiconductor device is mounted to a first insulated metal substrate, the first semiconductor device configured from a III-N semiconductor material. A first electrical interconnect is coupled between the first current carrying terminal of the first semiconductor device and a second portion of the die receiving area. In accordance with another embodiment, method includes providing a first semiconductor chip comprising a III-N semiconductor substrate material and a second semiconductor chip comprising a silicon based semiconductor substrate. The first semiconductor chip is mounted on a first substrate and the second semiconductor chip on a second substrate. The first semiconductor chip is electrically coupled to the second semiconductor chip.