III-N Transistors with Graded Dopants for Monolithic CMOS
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Solution Overview
Problem
The implementation of III-N transistors in high-frequency and high-voltage applications is limited by the absence of viable low-voltage P-type metal-oxide-semiconductor (PMOS) transistors, necessitating separate chips for N-type metal-oxide-semiconductor (NMOS) and PMOS transistors, which increases complexity and reduces viability due to the need for multiple input/output pins.
Innovation Solution
Integration of thin-film transistors (TFTs) with III-N transistors on the same support structure, utilizing graded dopant concentrations in source/drain regions and channel regions, and thicker/composite gate dielectrics to enable monolithic integration of PMOS and NMOS transistors, allowing for complementary metal-oxide-semiconductor (CMOS) circuit solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If III-N transistors are used in high-frequency and high-voltage applications, then performance is improved, but the absence of viable low-voltage PMOS transistors prevents monolithic integration
Solution Approach 1:
The patent merges PMOS and NMOS transistors into a single monolithic III-N transistor device, enabling CMOS logic functionality on one chip. This is achieved by integrating multiple transistor types with different threshold voltages within the same III-N semiconductor structure, allowing both high-frequency/high-voltage operation and low-voltage logic control.
Solution Approach 2:
The patent applies local quality by creating regions with different dopant concentrations and threshold voltages within the III-N transistor structure. Specific regions are engineered to function as high-voltage switches while other regions operate as low-voltage logic elements, enabling both PMOS and NMOS behavior in a unified III-N device.
2Adaptability or versatility
If separate chips are used for NMOS and PMOS transistors, then device functionality is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines multiple transistor functions into a single monolithic III-N device, eliminating the need for separate NMOS and PMOS chips. This integration simplifies manufacturing by reducing the number of fabrication processes, alignment steps, and packaging operations required to produce functional CMOS circuits.
Solution Approach 2:
The III-N transistor structure is designed to perform multiple functions simultaneously - serving as both high-voltage switching element and low-voltage logic element. This multi-functionality is achieved through carefully engineered dopant profiles and threshold voltage control, allowing a single device type to replace multiple specialized transistor types.
3Adaptability or versatility
If multiple chips are integrated with multiple input/output pins, then device functionality is achieved, but the number of input/output pins increases
Solution Approach 1:
The patent merges multiple transistor functions into a single monolithic device, which directly reduces the number of external input/output pins required. By integrating PMOS and NMOS functionality within one chip, the patent eliminates the need for inter-chip connections and reduces the pin count required for circuit operation.
Data Source
AI summary
Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N devices, e.g., III-N transistors. In various aspects, TFTs integrated with III-N transistors have a channel and source/drain materials that include one or more of a crystalline material, a polycrystalline semiconductor material, or a laminate of crystalline and polycrystalline materials. In various aspects, TFTs integrated with III-N transistors are engineered to include one or more of 1) graded dopant concentrations in their source/drain regions, 2) graded dopant concentrations in their channel regions, and 3) thicker and/or composite gate dielectrics in their gate stacks.