Integrated III-Nitride Cascode Layout for Reliable E-Mode Switching
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Solution Overview
Problem
Reliable fabrication and manufacturing of high-voltage III-N enhancement-mode (E-mode) transistors have proven to be difficult, necessitating the use of hybrid devices combining high-voltage depletion-mode (D-mode) III-N transistors with low-voltage E-mode transistors in cascode configurations.
Innovation Solution
The integration of a low-voltage enhancement-mode device and a high-voltage depletion-mode III-N device into a single electronic component package forms a hybrid device, which can operate similarly to a single high-voltage E-mode III-N transistor, achieving comparable output characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single high-voltage enhancement-mode III-N transistor is fabricated, then the device can operate with normally-off characteristics and positive threshold voltage, but the fabrication and manufacturing reliability is very difficult to achieve
Solution Approach 1:
The patent divides the high-voltage enhancement-mode transistor into two separate transistors: a low-voltage enhancement-mode III-N transistor and a high-voltage depletion-mode III-N transistor connected in cascode configuration. This segmentation allows each transistor to be optimized for its specific voltage range, making fabrication and manufacturing more reliable while achieving the desired normally-off high-voltage operation
Solution Approach 2:
The patent combines two III-N transistors (low-voltage enhancement-mode and high-voltage depletion-mode) into a single integrated cascode device. This merging integrates the benefits of both transistor types into one component that delivers normally-off high-voltage operation with improved fabrication reliability compared to attempting to fabricate a single high-voltage enhancement-mode transistor
2Ease of manufacture
If a hybrid device combining low-voltage enhancement-mode and high-voltage depletion-mode transistors is used, then the assembly complexity and cost are reduced, but the device must be integrated into a single package
Solution Approach 1:
The patent merges the low-voltage enhancement-mode transistor and high-voltage depletion-mode transistor into a single integrated package with shared terminals and interconnected structures. This integration reduces assembly complexity by eliminating the need for separate packaging and interconnection of discrete devices, while the cascode configuration simplifies the overall device architecture
Solution Approach 2:
The patent implements a nested structure where the low-voltage enhancement-mode transistor is positioned and electrically connected to the high-voltage depletion-mode transistor within a single package. The source of the enhancement-mode transistor connects to the drain of the depletion-mode transistor, creating a compact nested arrangement that reduces assembly complexity
Data Source
AI summary
A semiconductor device comprises a III-N device and a Field Effect Transistor (FET). The III-N device comprises a substrate on a first side of a III-N material structure, a first gate, a first source, and a first drain on a side of the III-N material structure opposite the substrate. The FET comprises a second semiconductor material structure, a second gate, a second source, and a second drain, and the second source being on an opposite side of the second semiconductor material structure from the second drain. The second drain of the FET is directly contacting and electrically connected to the first source of the III-N devices, and a via-hole is formed through a portion of the III-N material structure exposing a portion of the top surface of the substrate and the first gate is electrically connected to the substrate through the via-hole.