Integrated III-Nitride Cascode Layout for Normally-Off High Voltage
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Solution Overview
Problem
Reliable fabrication and manufacturing of high-voltage enhancement-mode III-Nitride (III-N) transistors have proven difficult, with conventional approaches often requiring complex cascode configurations involving both high-voltage depletion-mode and low-voltage enhancement-mode transistors to achieve similar output characteristics.
Innovation Solution
An integrated semiconductor device design that combines a low-voltage enhancement-mode transistor with a high-voltage depletion-mode III-N transistor in a single package, forming a hybrid device capable of operating similarly to a single high-voltage enhancement-mode transistor, with the depletion-mode transistor having a larger breakdown voltage and the enhancement-mode transistor having a lower breakdown voltage, arranged in a cascode configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single high-voltage enhancement-mode III-N transistor is fabricated, then normally-off operation and high-voltage capability are achieved, but manufacturing reliability is poor
Solution Approach 1:
The patent segments the high-voltage transistor functionality into two separate transistors: a low-voltage enhancement-mode device and a high-voltage depletion-mode device, connected in cascode configuration. This segmentation allows each transistor to be optimized for its specific voltage range, improving manufacturing reliability while achieving the overall high-voltage normally-off operation through the series connection of the two devices.
Solution Approach 2:
The patent employs a hybrid composite structure combining two different transistor types (enhancement-mode and depletion-mode) with different voltage ratings. This composite cascode configuration leverages the complementary strengths of each transistor type to achieve reliable high-voltage normally-off operation that is difficult to obtain with a single device type.
2Reliability
If a cascode configuration with both high-voltage depletion-mode and low-voltage enhancement-mode transistors is used, then normally-off high-voltage operation is achieved, but assembly complexity increases
Solution Approach 1:
The patent merges the low-voltage enhancement-mode transistor and high-voltage depletion-mode transistor into a single integrated cascode device package. By combining these two transistors with complementary connections (source of HVDM to drain of LVEH, gate of LVEH to source lead, gate of HVDM to drain lead), the patent achieves reliable normally-off high-voltage operation while reducing assembly complexity compared to separate discrete components.
3Reliability
If a hybrid cascode device is packaged, then high-voltage blocking capability is achieved, but manufacturing cost increases
Solution Approach 1:
The patent creates a universal hybrid cascode device that can be used in various high-voltage power electronics applications requiring normally-off operation. By designing the device with standardized packaging and integrated connections that accommodate both transistor types, the patent achieves high-voltage blocking capability while reducing manufacturing cost through design standardization and simplified assembly procedures.
Data Source
AI summary
A semiconductor device comprises a III-N device and a Field Effect Transistor (FET). The III-N device comprises a substrate on a first side of a III-N material structure, a first gate, a first source, and a first drain on a side of the III-N material structure opposite the substrate. The FET comprises a second semiconductor material structure, a second gate, a second source, and a second drain, and the second source being on an opposite side of the second semiconductor material structure from the second drain. The second drain of the FET is directly contacting and electrically connected to the first source of the III-N devices, and a via-hole is formed through a portion of the III-N material structure exposing a portion of the top surface of the substrate and the first gate is electrically connected to the substrate through the via-hole.