Integrated III-Nitride and FET Layout for High-Voltage E-Mode Switching
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Solution Overview
Problem
Reliable fabrication and manufacturing of high-voltage enhancement-mode (E-mode) III-Nitride transistors is difficult, and existing hybrid devices with a combination of high-voltage depletion-mode (D-mode) and low-voltage E-mode transistors face challenges in reducing complexity and cost while maintaining performance.
Innovation Solution
Integration of a low-voltage enhancement-mode transistor and a high-voltage depletion-mode transistor into a single electronic component package, eliminating the need for external connectors and ceramic substrates, and optimizing the III-N material structure for high-voltage applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hybrid device combining high-voltage D-mode and low-voltage E-mode transistors is used, then the device can achieve high-voltage blocking capability and normally-off operation, but the device complexity and manufacturing cost increase due to requiring external connectors and ceramic substrates
Solution Approach 1:
The patent integrates the high-voltage D-mode III-N transistor and low-voltage E-mode transistor into a single monolithic device structure where the transistors share common substrates and interconnect layers. This merging eliminates the need for external connectors and ceramic substrates, reducing package complexity while maintaining the hybrid device's high-voltage blocking capability and normally-off operation
Solution Approach 2:
The shared substrate and interconnect structure serves multiple functions simultaneously: it provides mechanical support, electrical interconnection between the D-mode and E-mode transistors, and thermal management. This multi-functionality reduces the number of separate components needed, thereby reducing device complexity and manufacturing cost
2Adaptability or versatility
If a hybrid device with separate transistors is used, then the device can provide high-voltage and low-voltage functionality, but the manufacturing cost increases due to requiring ceramic substrates and external connectors
Solution Approach 1:
The patent combines both high-voltage and low-voltage transistor functionalities into a single integrated structure that shares common manufacturing processes, substrates, and interconnect layers. This merging eliminates the need for separate ceramic substrates and external connectors, significantly reducing manufacturing cost while preserving both high-voltage and low-voltage functionality
Solution Approach 2:
The patent uses parameter changes in the semiconductor material structure, such as varying the thickness and composition of III-N material layers, to achieve both high-voltage and low-voltage device characteristics within the same integrated structure. This allows versatile functionality to be achieved through material parameter optimization rather than through complex multi-component assembly
3Ease of operation
If conventional hybrid devices with external connectors are used, then the device can operate as a high-voltage switch, but the device size and parasitic inductance increase
Solution Approach 1:
The patent merges the high-voltage D-mode transistor and low-voltage E-mode transistor into a closely integrated monolithic structure, eliminating the need for external connectors and ceramic substrates. This integration dramatically reduces the overall device volume while maintaining the ability to operate as a high-voltage switch with low parasitic inductance
Data Source
AI summary
A semiconductor device comprises a III-N device and a Field Effect Transistor (FET). The III-N device comprises a substrate on a first side of a III-N material structure, a first gate, a first source, and a first drain on a side of the III-N material structure opposite the substrate. The FET comprises a second semiconductor material structure, a second gate, a second source, and a second drain, and the second source being on an opposite side of the second semiconductor material structure from the second drain. The second drain of the FET is directly contacting and electrically connected to the first source of the III-N devices, and a via-hole is formed through a portion of the III-N material structure exposing a portion of the top surface of the substrate and the first gate is electrically connected to the substrate through the via-hole.