III-Nitride Gate Bus Layout for Low Resistance and Capacitance
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Solution Overview
Problem
Existing semiconductor devices face challenges in maintaining low overall gate resistance and reducing parasitic capacitance, especially when operating at high voltage and frequency levels.
Innovation Solution
The semiconductor device incorporates a III-nitride layer, a gate, a connection structure, and a gate bus, where the gate bus is electrically connected to the gate through the connection structure, allowing for a parallel configuration that maintains low resistance and reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate structure is used, then the device structure is simple, but the gate resistance is high and parasitic capacitance is increased
Solution Approach 1:
The gate structure is segmented into multiple components: gate electrode, connection structure, and gate bus. The connection structure divides the gate electrode into multiple regions, creating multiple parallel conduction paths that reduce overall gate resistance while maintaining a manageable structural complexity through modular design.
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional configuration by adding the gate bus extending in a direction substantially perpendicular to the gate electrode. This dimensional change allows the gate bus to connect to multiple divided regions of the gate electrode, reducing parasitic capacitance by increasing spatial separation between conductive elements.
2Reliability
If the gate bus is directly connected to the gate electrode, then the connection is simple, but the parasitic capacitance is increased
Solution Approach 1:
The connection structure serves as an intermediary element between the gate electrode and the gate bus. It divides the gate electrode into multiple regions and provides multiple connection points, thereby reducing parasitic capacitance through increased spatial separation while maintaining electrical connectivity. The intermediary structure manages the complexity by organizing connections in a systematic manner.
3Reliability
If a parallel configuration with connection structure is used, then the gate resistance is reduced, but the device complexity increases
Solution Approach 1:
The parallel configuration segments the gate electrode into multiple regions through the connection structure, creating multiple independent conduction paths. This segmentation reduces gate resistance by providing alternative current paths while organizing the increased structural complexity into a systematic, modular architecture that is manageable in fabrication and design.
Data Source
AI summary
The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-nitride layer, a gate, a connection structure, and a gate bus. The gate is disposed over the III-nitride layer. The connection structure is disposed over the gate. The gate bus extends substantially in parallel to the gate and disposed over the connection structure from a top view perspective. The gate bus is electrically connected to the gate through the connection structure.