III-Nitride Power Device Gate Charge Engineering
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional III-nitride power semiconductor devices face issues with high electric field build-up near the gate, leading to gate breakdown, low drain-source breakdown voltage, and time-dependent degradation due to hot carriers and charge trapping, which are exacerbated by the use of field plates that increase active area and switching losses.
Innovation Solution
The introduction of a reduced charge region under the gate arrangement, which is less conductive than adjacent regions, reduces peak electric fields at the gate edges and corners, allowing for the omission of field plates and maintaining low parasitic source-drain series resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a field plate is provided to reduce electric field intensity at the gate edge, then breakdown voltage is improved, but active area increases and switching losses increase
Solution Approach 1:
The patent applies local quality by creating a reduced charge region specifically at the gate edge where high electric field occurs, rather than using a field plate across the entire gate. This localized modification reduces peak electric field intensity at the critical area while maintaining low charge concentration elsewhere, thereby improving breakdown voltage without significantly increasing active area or switching losses
Solution Approach 2:
The patent changes the charge concentration parameter locally at the gate edge by forming a reduced charge region with lower mobile charge concentration compared to the bulk 2-DEG channel. This parameter change reduces the peak electric field intensity at the gate edge, improving breakdown voltage without requiring a field plate structure that would increase switching losses
2Reliability
If a field plate is provided to reduce electric field intensity at the gate edge, then breakdown voltage is improved, but device area increases
Solution Approach 1:
The patent applies local quality by creating a reduced charge region specifically at the gate edge where high electric field occurs, rather than using a field plate across the entire gate. This localized modification reduces peak electric field intensity at the critical area without significantly increasing the overall device active area
Solution Approach 2:
The patent extracts the field plate structure entirely and replaces it with a reduced charge region formed by selective charge concentration reduction at the gate edge. This extraction eliminates the need for additional field plate area while still achieving the goal of reducing peak electric field intensity and improving breakdown voltage
3Reliability
If mobile charge concentration is reduced under the gate, then peak electric field is reduced, but channel conductivity decreases
Solution Approach 1:
The patent applies local quality by reducing mobile charge concentration only at the gate edge region where peak electric field occurs, while maintaining high charge concentration in the bulk channel region. This localized differentiation allows peak electric field reduction for improved reliability without significantly degrading overall channel conductivity for power transmission
Solution Approach 2:
The patent applies partial action by reducing charge concentration only in the specific region under the gate edge where it is most needed for field control, rather than reducing it uniformly across the entire channel. This partial modification achieves the necessary peak field reduction while minimizing the impact on overall channel conductivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces electric field strength at the gate edges, enhancing breakdown voltage and switching performance by minimizing charge concentration under the gate, thereby reducing switching losses and omitting the need for field plates.
Implementation Method 1
the composition and thickness of each III-nitride semiconductor body 12, 14 is selected to generate a two-dimensional electron gas 16 (2-DEG) at the heterojunction of the two bodies 12, 14
Data Source
AI summary
A power semiconductor device includes a III-nitride heterojunction body including a first III-nitride body and a second III-nitride body having a different band gap than that of the first III-nitride body, a first power electrode coupled to the second III-nitride body, a second power electrode coupled to the second III-nitride body, a gate arrangement disposed between the first and second power electrodes, and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under the gate arrangement that is less conductive than its adjacent regions. The reduced charge region extends beyond an edge of the gate arrangement toward one of the power electrodes only.