III-Nitride Heterojunction Device Gate Segmentation
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Solution Overview
Problem
Current semiconductor devices face challenges in managing switch mode power supplies due to high losses associated with resistance and gate charge, particularly at higher frequencies and high currents, where reducing gate charge affects threshold voltage and resistance, making it difficult to optimize device size for performance.
Innovation Solution
The approach involves reducing gate area by interrupting conduction under the gate, which decreases gate capacitance and conductivity with minimal impact on resistance, allowing independent tuning of threshold voltage, gate charge, and device resistance without altering the total ohmic contact area or changing the charge density under the gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the gate area is reduced by interrupting conduction under the gate, then gate capacitance and conductivity are decreased, but device resistance may increase
Solution Approach 1:
The gate area is segmented into multiple discrete gate fingers or gate segments separated by trenches or isolation regions. This segmentation reduces the total gate capacitance and gate charge while maintaining effective channel control. The segmented structure allows the gate to influence the channel through electric field effects rather than direct continuous contact, thereby reducing capacitive coupling and associated charging losses.
Solution Approach 2:
The channel region under the gate is modified to have different local properties - specifically, the channel width or carrier density is adjusted in the regions directly under the gate segments compared to the regions between segments. This local quality change allows the gate to control channel conductivity through field effects while the overall device resistance is managed by optimizing the channel geometry and material composition in different regions.
2Use of energy by moving object
If blanket gate charge density reduction is applied, then threshold voltage and capacitance are reduced, but device resistance increases and manufacturing precision deteriorates
Solution Approach 1:
Rather than applying a blanket reduction of gate charge density across the entire gate area, the invention segments the gate structure into discrete fingers or regions. This segmentation allows precise control of threshold voltage through geometric parameters (gate finger width, spacing, length) rather than relying on difficult-to-control charge density modifications. The segmented approach transforms the control mechanism from material property adjustment to geometric configuration, improving manufacturing precision.
Solution Approach 2:
The invention changes the control parameter from gate charge density (which is difficult to control with 10-20% variation) to geometric parameters such as gate finger width, spacing, and length. These geometric parameters can be controlled with much higher precision during fabrication. By changing the control mechanism from material composition/charge density to geometry, the invention achieves better manufacturing precision and more consistent threshold voltage control.
3Loss of energy
If device width is increased to reduce resistance, then resistive losses decrease, but gate charge increases
Solution Approach 1:
The device width is segmented into multiple parallel gate fingers rather than using a single continuous gate. This segmentation allows the channel width to be increased for lower resistance while the gate structure itself remains segmented and compact. The total gate charge is reduced because each gate finger has smaller capacitance to the channel, and the segmented structure reduces parasitic capacitances. The effective channel width for current conduction is increased while the gate control structure is optimized to minimize charging requirements.
Solution Approach 2:
The invention transitions from a planar gate structure to a three-dimensional segmented configuration. By arranging multiple gate fingers in parallel with specific spacing, the effective channel width is increased in one dimension while the gate charge is controlled through the vertical and lateral dimensions of individual fingers. This dimensional approach allows independent optimization of resistance (through channel width) and gate charge (through gate finger geometry).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the fabrication process and reduces process influence on device characteristics, enabling more precise control over device performance by maintaining consistent threshold voltage and resistance while minimizing resistive and switching losses.
Implementation Method 1
a two-dimensional gas (2-DEG) over the entire wafer during the formation of the III-nitride heterojunction
Implementation Method 2
first AlGaN layer and a second AlGaN layer having a different aluminum composition than the first AlGaN layer
Implementation Method 3
instead of reducing the charge under the gate to reduce the gate charge, the gate area is reduced by interrupting conduction under the gate
Data Source
AI summary
A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.