III-Nitride Semiconductor Die Fabrication via Grid Array Trenches
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Solution Overview
Problem
The deposition of III-Nitride films on non-native substrates often results in excessive wafer warpage, cracking, and delamination due to lattice constant mismatches and differences in thermal expansion coefficients, which existing approaches have not adequately addressed.
Innovation Solution
The implementation of grid array trenches aligned with saw streets on the semiconductor wafer to reduce stress and prevent delamination and cracking, by etching trenches in the III-Nitride body that extend through device layers and substrate, thereby inhibiting the propagation of stress-induced cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If III-Nitride films are deposited on non-native substrates, then device functionality is achieved, but excessive wafer warpage and bow occur due to lattice constant mismatches and thermal expansion differences
Solution Approach 1:
The patent introduces a grid array of control joints that segment the continuous III-Nitride film into discrete regions. These joints create a segmented structure that allows independent stress relief in each grid cell, preventing cumulative stress buildup across the entire wafer surface while maintaining the overall film functionality.
Solution Approach 2:
The control joints act as intermediary elements between the III-Nitride film and the non-native substrate. These joints serve as stress mediators that decouple the thermal expansion mismatch and lattice constant differences between the film and substrate, allowing the film to maintain adhesion while accommodating dimensional changes during processing.
2Adaptability or versatility
If III-Nitride films are deposited on non-native substrates, then device functionality is achieved, but deleterious cracking and delamination occur due to stress accumulation
Solution Approach 1:
The grid array of control joints segments the III-Nitride film into discrete regions, preventing crack propagation across the entire wafer. Each grid cell acts as an independent stress containment zone, so that cracks are confined to individual cells rather than propagating through the whole film, thereby maintaining overall film integrity.
Solution Approach 2:
The control joints are pre-formed in the III-Nitride film before device fabrication and stress accumulation occurs. These joints serve as pre-positioned stress relief features that cushion against future thermal and mechanical stresses, preventing crack initiation and delamination before they can occur during subsequent processing steps.
3Stress or pressure
If control joints are formed in the non-native substrate prior to growth, then stress buildup is reduced, but additional manufacturing steps and process complexity are required
Solution Approach 1:
The control joints are formed in the III-Nitride film after epitaxial growth but before device fabrication and stress accumulation. This timing allows the joints to be created when the film is already adhered to the substrate, maximizing stress relief effectiveness while integrating the process into the existing fabrication sequence without requiring separate substrate preparation steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces stress on III-Nitride films, preventing delamination and cracking during processing and handling, such as dicing, and maintains wafer integrity.
Implementation Method 1
etching grid array trenches in a III-Nitride body to form a grid array
Data Source
AI summary
According to an embodiment of a method of fabricating III-Nitride semiconductor dies, the method includes: growing a III-Nitride body over a group IV substrate in a semiconductor wafer; forming at least one device layer over the III-Nitride body; etching grid array trenches in the III-Nitride body and in the group IV substrate; forming an edge trench around a perimeter of the semiconductor wafer, the grid array trenches terminating inside the group IV substrate; and forming separate dies by cutting the semiconductor wafer approximately along the grid array trenches.