III-Nitride Half-Bridge Module Layout for Low-EMI High-Voltage Switching
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Solution Overview
Problem
The reliable fabrication and operation of high-voltage enhancement-mode III-Nitride (III-N) transistors are challenging, and existing solutions like cascode configurations with silicon E-mode FETs increase complexity and cost due to hard-switching issues and high electromagnetic interference (EMI) in power switching circuits.
Innovation Solution
Integration of a low-voltage enhancement-mode and a high-voltage depletion-mode III-N device into a single electronic component module forms half-bridge and full-bridge power switching circuits, utilizing a cascode configuration with direct bonding of copper substrates to reduce parasitic inductance and enhance switching speed and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If high-voltage enhancement-mode III-N transistors are fabricated, then high voltage blocking capability is achieved, but fabrication reliability deteriorates
Solution Approach 1:
The transistor is segmented into two distinct modes: a depletion-mode III-N transistor for high-voltage blocking and an enhancement-mode transistor for reliable switching control. This segmentation allows each part to optimize its function independently, achieving high voltage capability while maintaining fabrication reliability through the use of well-established enhancement-mode fabrication processes.
Solution Approach 2:
The invention uses a composite transistor structure combining depletion-mode and enhancement-mode characteristics. The depletion-mode III-N layer provides high-voltage blocking, while the enhancement-mode structure enables reliable fabrication and control, creating a hybrid device that leverages the advantages of both modes.
2Stress or pressure
If cascode configuration with silicon E-mode FETs is used, then high-voltage enhancement-mode operation is achieved, but device complexity increases
Solution Approach 1:
The invention merges the depletion-mode high-voltage blocking function and enhancement-mode switching control function into a single integrated transistor device. This unified structure eliminates the need for separate cascode connections between different transistor types, reducing device complexity while maintaining high-voltage capability.
Solution Approach 2:
The transistor combines depletion-mode and enhancement-mode characteristics within a single device structure using III-N semiconductor materials. This composite approach achieves high-voltage operation without requiring external cascode configurations, simplifying the overall device architecture.
3Speed
If hard-switching is used in power switching circuits, then switching speed is improved, but electromagnetic interference increases
Solution Approach 1:
The invention changes the switching parameters by using an enhancement-mode transistor with positive threshold voltage, which enables controlled turn-on and turn-off operations. This parameter change allows for softer switching transitions that maintain fast switching speeds while reducing electromagnetic interference compared to traditional depletion-mode hard-switching.
Solution Approach 2:
The enhancement-mode transistor structure provides inherent feedback control through its gate voltage dependency. The device only conducts when sufficient gate voltage is applied, enabling controlled switching that reduces electromagnetic interference while maintaining fast switching performance through precise voltage control.
Data Source
AI summary
An electronic module for a half-bridge circuit includes a base substrate with an insulating layer between a first metal layer and a second metal layer. A trench formed through the first metal layer electrically isolates first, second, and third portions of the first metal layer from one another. A high-side switch includes an enhancement-mode transistor and a depletion-mode transistor. The depletion-mode transistor includes a III-N material structure on an electrically conductive substrate. A drain electrode of the depletion-mode transistor is connected to the first portion, a source electrode of the enhancement-mode transistor is connected to the second portion, a drain electrode of the enhancement-mode transistor is connected to a source electrode of the depletion-mode transistor, a gate electrode of the depletion-mode transistor is connected to the electrically conductive substrate, and the electrically conductive substrate is connected to the second portion.