III-Nitride Rectifier Package Using Conductive Clips
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Solution Overview
Problem
Conventional package integration techniques for combining III-nitride transistors with silicon diodes in high power and high performance circuit applications result in increased package form factor, manufacturing costs, parasitic inductance, resistance, and thermal dissipation requirements, while also requiring expensive fabrication facilities.
Innovation Solution
A high voltage cascoded III-nitride rectifier package utilizing conductive clips on a package support surface, eliminating the need for wire bonds and allowing for a compact, cost-effective integration of III-nitride transistors and silicon diodes, with a physical separation between anode and cathode of 2.7500 mm or greater to accommodate high voltage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used for terminal connections in conventional package designs, then electrical connections can be established, but package form factor increases, parasitic inductance and resistance increase, and manufacturing costs increase
Solution Approach 1:
The patent removes wire bonds from the package structure entirely, replacing them with direct solder connections between the semiconductor die and package leads. This extraction of the wire bond element eliminates the associated parasitic inductance, resistance, and space requirements while maintaining electrical connectivity through the solder joints.
Solution Approach 2:
The patent introduces solder as an intermediary material that directly connects the semiconductor die terminals to the package leads. This intermediary replaces the wire bond function while enabling a more compact integration scheme where the solder joint serves both as mechanical support and electrical connection, reducing overall package size and parasitics.
2Reliability
If wire bonds are used for terminal connections, then electrical connections can be established, but parasitic inductance and resistance increase
Solution Approach 1:
The patent removes wire bonds from the package structure entirely, replacing them with direct solder connections between the semiconductor die and package leads. This extraction of the wire bond element eliminates the associated parasitic inductance, resistance, and space requirements while maintaining electrical connectivity through the solder joints.
Solution Approach 2:
The patent transitions from a three-dimensional wire bond connection (extending vertically from die to lead) to a planar solder joint connection (lying flat between die and lead). This dimensional change reduces the current path length and loop area, thereby minimizing parasitic inductance and resistance while maintaining reliable electrical connection.
3Reliability
If wire bonds are used for terminal connections, then electrical connections can be established, but thermal dissipation requirements increase
Solution Approach 1:
The patent removes wire bonds from the package structure entirely, replacing them with direct solder connections between the semiconductor die and package leads. This extraction of the wire bond element eliminates the associated parasitic inductance, resistance, and space requirements while maintaining electrical connectivity through the solder joints.
Solution Approach 2:
The patent transitions from a three-dimensional wire bond connection (extending vertically from die to lead) to a planar solder joint connection (lying flat between die and lead). This dimensional change reduces the current path length and loop area, thereby minimizing parasitic inductance and resistance while maintaining reliable electrical connection.
Data Source
AI summary
Some exemplary embodiments of high voltage cascoded III-nitride semiconductor package utilizing clips on a package support surface have been disclosed. One exemplary embodiment comprises a III-nitride transistor attached to a package support surface and having an anode of a diode stacked over a source of the III-nitride transistor, a first conductive clip coupled to a gate of the III-nitride transistor and the anode of the diode, and a second conductive clip coupled to a drain of the III-nitride transistor. The conductive clips are connected to the package support surface and expose respective flat portions that are surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since a low cost printed circuit board (PCB) may be utilized for the package support surface, expensive leadless fabrication processes may be avoided for cost effective manufacturing.


