III-Nitride RF Transistor Metallization With Cavities for Lower Capacitance
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Solution Overview
Problem
Current Group III nitride RF power devices face limitations in achieving fast switching times due to high device terminal and inter-metallization capacitances, which affect their performance and energy efficiency.
Innovation Solution
The introduction of a multilayer Group III nitride-based semiconductor device with a metallization structure that includes electrically insulating layers and conductive redistribution structures, featuring cavities or voids to reduce parasitic capacitances, achieved by using tungsten and copper for conductive layers and vias, and dielectric materials like silicon oxide or nitride, which are partially removed to create low-k dielectric media in high electric field regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metallization structures are used in Group III nitride RF power devices, then device terminal and inter-metallization capacitances are high, but manufacturing is simpler
Solution Approach 1:
The metallization structure is segmented into multiple functional layers: conductive redistribution layers for electrical connection, electrically insulating layers for isolation, and cavity structures for capacitance reduction. This segmentation allows each layer to perform its specific function optimally, resolving the contradiction between performance and complexity by organizing complexity into manageable, functional segments.
Solution Approach 2:
The patent applies local quality by creating cavities (voids) specifically in regions where electric field intensity is highest, such as between closely spaced metallization fingers. This localized modification reduces parasitic capacitance only where it most impacts performance, rather than uniformly throughout the entire device, thus improving switching time without unnecessarily complicating the overall structure.
2Reliability
If dielectric material is removed to create cavities, then parasitic capacitances are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The cavity formation is performed as a preliminary action during the metallization structure fabrication process, before final device assembly. By creating cavities early in the process when the structure is still being built, the patent integrates what would otherwise be a separate, precision-critical step into the existing fabrication flow, reducing the need for additional high-precision operations.
Solution Approach 2:
The cavity structures are nested within the metallization structure, with voids positioned between conductive layers and within insulating layers. This nesting approach allows the cavities to be formed using the same layer deposition and patterning processes already required for the metallization structure itself, rather than requiring separate precision operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces capacitances such as Cds, Cgd, and Cgs, enhancing the high-frequency performance and energy efficiency of RF Power III-N Transistors by creating effective low-k dielectric media within the metallization structure, thereby improving the performance and manufacturability of RF Power devices.
Implementation Method 1
One or more cavities are located in the electrically insulating layer of the metallization structure... The content of the cavity, e.g. the gas or vacuum and consequently the cavity has a dielectric constant that is lower than a dielectric constant of the electrically insulating layer... Reduction of dielectric constant can be e.g. a reduction from k=3.7 to k=1.0 in the case where SiO2 is replaced by a gas or vacuum.
Implementation Method 2
The provision of void or cavity structures which are integrated in the metallization structure is used to reduce the capacitance of the Group III nitride-based semiconductor device... reduce parasitic fringing capacitances.
Data Source
AI summary
In an embodiment, a Group III nitride-based semiconductor device includes: a multilayer Group III nitride-based structure including a first major surface; and a source electrode, a gate electrode and a drain electrode arranged on the first major surface. The gate electrode is laterally arranged between the source electrode and the drain electrode and a metallization structure arranged on the first major surface. The metallization structure includes an electrically insulating layer arranged on the source electrode, the gate electrode and the drain electrode and a conductive redistribution structure electrically connected to the source electrode, the gate electrode and the drain electrode. One or more cavities are located in the electrically insulating layer of the metallization structure.