III-Nitride Semiconductor Fabrication on Partial Isolated Silicon Substrate
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Solution Overview
Problem
The existing methods for fabricating III-nitride semiconductor devices on silicon substrates face issues such as suboptimal breakdown voltage and leakage current due to parasitic channels, increased thermal dissipation, and production challenges like substrate thinning and bowing, especially for large-scaled chips.
Innovation Solution
A method involving direct top etching of III-nitride based semiconductor devices on a partial isolated silicon substrate, where a diode device is formed with a nucleation layer, buffer layer, channel layer, and barrier layer, followed by selective etching to remove these layers and a part of the substrate, avoiding substrate thinning and transfer processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the Si substrate is completely etched out and the device is transferred to another insulating substrate, then the breakdown voltage and leakage current are significantly improved, but the thermal dissipation problem increases the on-state resistance and decreases the on-state output current
Solution Approach 1:
The patent applies partial etching of the Si substrate instead of complete removal. Specifically, a first etching process removes part of the Si substrate to eliminate parasitic channels and improve breakdown voltage, while a second etching process creates isolation trenches. This partial action maintains enough substrate to preserve thermal dissipation pathways, thus resolving the contradiction between improving reliability and maintaining temperature management.
2Ease of manufacture
If the Si substrate is made thin by being polished and/or etched to enable deep-etching, then the fabrication process can proceed, but the chip experiences serious bowing that may destroy the epitaxial structure and lower production yield
Solution Approach 1:
The patent performs preliminary thinning of the Si substrate through controlled etching processes before subsequent fabrication steps. By pre-establishing the appropriate substrate thickness and isolation structures, the method prevents bowing issues that would otherwise occur during deep-etching operations, thereby maintaining manufacturing precision while enabling the fabrication process to proceed.
3Manufacturing precision
If deep-etching is performed on the Si substrate to remove parasitic channels, then the line width can be controlled, but the fabrication procedure becomes complex and the bowing problem worsens
Solution Approach 1:
The patent segments the etching process into distinct stages: a first etching process for removing parasitic channels and a second etching process for creating isolation trenches. This segmentation allows each process to be optimized independently for line width control while maintaining overall procedure manageability, reducing the complexity that would arise from a single deep-etching operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances breakdown voltage, reduces leakage current, simplifies the fabrication process, and is compatible with modern procedures, allowing for the production of large-scaled chips with improved thermal dissipation and cost-effectiveness.
Implementation Method 1
directly etching a chip from top without substrate transferring technique or deep-etching a silicon (Si) substrate from back-side
Data Source
AI summary
A semiconductor is fabricated on a silicon (Si) substrate. The semiconductor is III-nitride based. The Si substrate is partially isolated. Etching is directly processed from top on a chip for solving wire-width problem. The Si substrate does not need to be made thin. The chip can be large scaled and be prevented from bowing. Thus, the present invention simplifies producing procedure and reduces production cost. Besides, for a large-scaled chip, the breakdown voltage is enhanced; and, without making the Si substrate thin, the on-state current is remained the same and the heat problem is weakened.