III-Nitride Semiconductor Structure with Selectively Etchable Spacer Layers

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Solution Overview

Problem

Current dry plasma etching techniques for forming gate recesses in III-Nitride transistors suffer from plasma-induced damage and etch-based process variations, making it difficult to achieve precise control over recess depth and threshold voltage, especially when integrating transistors with different threshold voltages on a common substrate.

Innovation Solution

A multi-layer semiconductor structure with selectively etchable layers and sublayers is used, employing a combination of dry and wet etching techniques to form gate recesses and ohmic recesses with controlled depths, reducing defect density and enabling precise control over threshold voltages by exploiting etching selectivity between different III-N semiconductor materials.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If dry plasma etching is used to form gate recesses, then the recesses can be formed in III-Nitride transistors, but plasma-induced damage and etch-based process variations occur, making it difficult to achieve precise control over recess depth and threshold voltage

Engineering Contradiction:
Improvecontrol over recess depthVSAvoidplasma-induced damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent segments the etching process into multiple selective etching steps using different etchants. First, a chlorine-based plasma etch removes the AlGaN barrier layer, then a sulfur-based plasma etch removes the GaN cap layer. This segmentation allows precise control over recess depth by independently controlling each etching step, while avoiding excessive plasma damage through selective removal of layers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary AlGaN barrier layer between the GaN channel and the GaN cap layer. This intermediary layer serves as a sacrificial layer that can be selectively removed by chlorine-based plasma etching before sulfur-based etching of the cap layer, enabling precise control over the gate recess depth and reducing direct plasma exposure damage to the channel region.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If dry plasma etching is used to form gate recesses, then the recesses can be formed, but etch-based process variations make it difficult to achieve precise control over threshold voltage, especially when integrating transistors with different threshold voltages on a common substrate

Engineering Contradiction:
Improveintegration of transistors with different threshold voltagesVSAvoidcontrol over threshold voltage
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by using different etchants with different selectivities for different layers. The chlorine-based plasma provides high selectivity for AlGaN over GaN, while the sulfur-based plasma provides high selectivity for GaN over AlGaN. This allows independent control of etching depth for each layer, enabling precise control over gate recess depth and threshold voltage for each transistor region, even when integrating transistors with different threshold voltages on the same substrate.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If a multi-layer semiconductor structure with selectively etchable layers is used, then precise control over recess depth can be achieved, but the device structure becomes more complex

Engineering Contradiction:
Improvecontrol over recess depthVSAvoidmulti-layer structure
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the functions of the AlGaN barrier layer and the GaN cap layer into a unified multi-layer structure that serves both device performance and etching control functions. The AlGaN barrier layer provides both electrical isolation and selective etching capability, while the GaN cap layer provides both surface protection and selective etching capability. This merging reduces the need for separate sacrificial layers and simplifies the overall fabrication process despite the multi-layer structure.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the monolithic integration of III-N transistors with different threshold voltages on a common substrate, enhancing performance, design flexibility, and reducing production costs by minimizing plasma damage and etch-based variations, while achieving precise control over recess depths and low defect densities.

Implementation Method 1

Chlorine-based dry plasma etching is typically used to form gate recesses in AlGaN/GaN devices

Methodology Applied
Scientific EffectPlasma etching: Plasma

Implementation Method 2

employing a combination of dry and wet etching techniques to form gate recesses and ohmic recesses with controlled depths, reducing defect density and enabling precise control over threshold voltages by exploiting etching selectivity between different III-N semiconductor materials

Methodology Applied
Scientific EffectChemical etching: Chemical Bonding

Data Source

PatentUS9536984B2Semiconductor structure with a spacer layer
Publication Date: 2017.01.03 FINWAVE SEMICONDUCTOR INC
  • US9536984B2 patent drawing
  • US9536984B2 patent drawing
  • US9536984B2 patent drawing

AI summary

A multi-layer semiconductor structure is disclosed for use in III-Nitride semiconductor devices, including a channel layer, a band-offset layer having a wider bandgap than the channel layer, a spacer layer having a narrower bandgap than the band-offset layer, and a cap layer comprising at least two sublayers. Each sublayer is selectively etchable with respect to sublayers immediately below and above, each sublayer comprises a III-N material AlxInyGazN in which 0≦x≦1, 0≦y≦1, and 0≦z≦1, at least one sublayer has a non-zero Ga content, and a sublayer immediately above the spacer layer has a wider bandgap than the spacer layer. Also described are methods for fabricating such semiconductor structures, with gate and/or ohmic recesses formed by selectively removing adjacent layers or sublayers. The performance of resulting devices is improved, while providing design flexibility to reduce production cost and circuit footprint.