III-V Anti-Fuse With High-k Dielectric Liner

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Solution Overview

Problem

The challenge in semiconductor manufacturing is to effectively integrate anti-fuses in III-V compound semiconductor material-based circuits to reduce defect levels and improve process efficiency, while existing methods struggle to efficiently form anti-fuses between different III-V compound semiconductor materials.

Innovation Solution

A semiconductor structure is developed with an anti-fuse positioned between a bottom and top III-V compound semiconductor material, utilizing a high-k dielectric material liner to separate the metal structures, and a method involving III-V aspect ratio trapping structures and selective epitaxial growth to create a gap for the anti-fuse formation, allowing for on-chip anti-fuse fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If anti-fuses are integrated in III-V compound semiconductor material-based circuits, then system integration and process efficiency are improved, but defect levels increase due to the complexity of forming anti-fuses between different III-V materials

Engineering Contradiction:
Improveprocess efficiencyVSAvoiddefect levels
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The anti-fuse structure is segmented into distinct regions: a first metal structure, a dielectric material layer, and a second metal structure. The middle region of the anti-fuse is specifically positioned in the gap between bottom and top III-V compound semiconductor materials, separating the metal structures and allowing independent formation processes for each component, thereby reducing defects while maintaining integration efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A dielectric material layer is introduced as an intermediary between the first and second metal structures. This dielectric layer acts as a separator and insulator, enabling the anti-fuse to be formed between different III-V compound semiconductor materials without direct metal-to-metal contact, thus reducing defect levels while maintaining system integration

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If a high-k dielectric material liner is used to separate metal structures, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improveanti-fuse formation precisionVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The dielectric material layer is applied selectively in the gap region between the bottom and top III-V compound semiconductor materials, specifically where the anti-fuse middle region is formed. This localized application provides precise separation and positioning for the anti-fuse structure without requiring complex modifications to the entire device architecture, thereby improving manufacturing precision with minimal increase in device complexity

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the efficient integration of anti-fuses, reducing defect levels and improving system integration by forming a conductive path between III-V compound semiconductor materials, enhancing the performance and reliability of semiconductor devices.

Implementation Method 1

A high-k dielectric material liner separates the second metal structure from a portion of the first metal structure

Methodology Applied
Scientific EffectDielectric: Dielectric

Implementation Method 2

III-V compound semiconductor materials typically require an aspect ratio trapping process to reduce defect levels to a reasonable number to manufacture high performance semiconductor devices

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9941204B2III-V compatible anti-fuses
Publication Date: 2018.04.10 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US9941204B2 patent drawing
  • US9941204B2 patent drawing
  • US9941204B2 patent drawing

AI summary

An anti-fuse is provided above a semiconductor material. The anti-fuse includes a first end region including a first metal structure; a second end region including a second metal structure; and a middle region located between the first end region and the second end region. In accordance with the present application, the middle region of the anti-fuse includes at least a portion of the second metal structure that is located in a gap positioned between a bottom III-V compound semiconductor material and a top III-V compound semiconductor material. A high-k dielectric material liner separates the second metal structure from a portion of the first metal structure.